ページ12に含まれる内容の要旨
AMD P R E L I M I N A R Y TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 PCMCIA Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ISA Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Memory Bus Interface Waveforms . . . .
ページ13に含まれる内容の要旨
PRELIMINARY PCMCIA CONNECTION DIAGRAM USER2 1 108 SAR0 USER3 2 SDSEL1 107 USER4 VSST 3 106 VDDM SDSEL2 4 105 XCE VDDT 104 5 MA11 SDSEL3 103 6 VSSM ADDATA 102 7 MA9 SDCLK 101 8 MA8 LNK 100 9 MA13 VSST 99 10 MWE ACT 98 11 MA14 VDDU1 97 12 MA16 USER5 96 13 MA15 USER6 95 14 MA12 RXC 94 15 VDDM VSSU1 93 16 V CC 92 USER7 17 MA7 91 USER1 18 MA6 Am79C930 90 USER0 19 MA5 89 V CC 20 VSSM 88 TDI 21 MA4 87 TRST 22 MA3 86 TMS 23 MA2 85 TDO 24 MA1 84 TCK 25 MA0 83 PMX1 26 MD0 82 PMX2 27 MD1 81 TEST 28 V
ページ14に含まれる内容の要旨
PRELIMINARY PCMCIA PIN SUMMARY Listed by Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 USER2 37 MA10 73 D7 109 SAR1 2 USER3 38 MOE 74 D6 110 SAR2 3 USER4 39 SCE 75 D5 111 SAR3 4 VDDM 40 FCE 76 VSSP 112 SAR4 5 XCE 41 D2 77 D4 113 SAR5 6 MA11 42 D1 78 D3 114 SAR6 7 VSSM 43 D0 79 PCMCIA 115 TXC 8 MA9 44 VSSP 80 CLK20 116 VSST 9 MA8 45 STSCHG 81 TEST 117 LFCLK 10 MA13 46 A0 82 PMX2 118 LFPE 11 MWE 47 A1 83 PMX1 119 HFCLK 12 MA14 48 REG 84 TCK 120 HFPE
ページ15に含まれる内容の要旨
PRELIMINARY PCMCIA PIN LIST Listed by Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. A0 46 HFPE 120 OE 70 TXMOD 131 A1 47 INPACK 50 PCMCIA 79 TXPE 129 A10 71 IORD 67 PMX1 83 USER0 90 A11 69 IOWR 66 PMX2 82 USER1 91 A12 56 IREQ 61 PWRDWN 133 USER2 1 A13 64 LFCLK 117 REG 48 USER3 2 A14 63 LFPE 118 RESET 58 USER4 3 A2 49 LLOCKE 144 RXC 94 USER5 96 A3 51 LNK 100 RXCIN 124 USER6 95 A4 53 MA0 26 RXDATA 123 V 17 CC A5 59 MA1 25 RXPE 122 V 89 CC A6 60 MA10 37
ページ16に含まれる内容の要旨
PRELIMINARY PCMCIA PIN FUNCTION SUMMARY PCMCIA Pin Summary No. of Pins Pin Name Pin Function Pin Style 15 A14–A0 PCMCIA address bus lines I 8 D7–D0 PCMCIA data bus lines TS2 1 RESET PCMCIA bus RESET line I Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write 1 CE1 I accesses Output Enable—used to enable the output drivers of the Am79C930 device for 1 OE I PCMCIA Read accesses 1 WE Write Enable—used to indicate that the current PCMCIA cycle is a write access I REG—used to
ページ17に含まれる内容の要旨
PRELIMINARY PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) No. of Pins Pin Name Pin Function Pin Style 1 TDO Test Data Out—this is the data output signal for IEEE 1149.1 testing TS1 1 TMS Test Mode Select—this is the test mode select for IEEE 1149.1 testing I 1 TRST Test Reset—this is the reset signal for IEEE 1149.1 testing I 1 USER7 User-programmable pin PTS3 1 RXC Receive Clock—provides decode receive clock PTS3 Test pin—when asserted, this pin places the Am79C9
ページ18に含まれる内容の要旨
PRELIMINARY PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) No. of Pins Pin Name Pin Function Pin Style 2 ADIN1–2 Comparator—A/D comparator inputs TS1 12 V Power I CC 13 GND Ground I User-definable I/O pins with direct accessibility and control through TCR and 7 USER0–USER6 PTS3, PTS1 TIR registers Output Driver Types Name Type I I Load OL OH TP1 Totem pole 4 mA –4 mA 50 pF TS1 Tri-state 4 mA –4 mA 50 pF TS2 Tri-state 24 mA –4 mA 120 pF PTS1 User-progra
ページ19に含まれる内容の要旨
PRELIMINARY ISA PLUG AND PLAY BLOCK DIAGRAM TRST JTAG TMS/T3 Control MOE TDI/T1 Block TDO/T2 MWE MA 16–0 MD 7–0 RXCIN ANTSLT XCE ANTSLT SAR6–0 SCE ADIN2–1 FCE ADREF RXDATA RXC LA23–17 SDCLK SA126–0 IEEE SDDATA SD7–0 802.11 SDSEL3–1 Network CA16–18 AEN TXCMD Interface Unit BALE CAD 7–0 DRQ0 TXCMD Bus IEEE MEMR TXMOD Interface Unit INT1 DRQ1 802.11 (ISA TXDATA IOR MAC ALE INT0 Plug and Play) Control Unit TXDATA IOW (80188 core) RXPE RESET WR RESET TXPE MEMW HFPE SRDY IOCHRDY HFCLK IRQ(X) LFPE
ページ20に含まれる内容の要旨
PRELIMINARY ISA PLUG AND PLAY CONNECTION DIAGRAM LA19 1 SAR0 108 SA16 SDSEL1 2 107 LA17 VSST 3 106 VDDM SDSEL2 105 4 XCE VDDT 5 104 MA11 SDSEL3 103 6 VSSM ADDATA 7 102 MA9 SDCLK 8 101 MA8 LNK 100 9 MA13 VSST 99 10 MWE ACT 98 11 MA14 VDDU1 97 12 MA16 IRQ4 96 13 MA15 IRQ5 95 14 MA12 IRQ10 94 15 VDDM VSSU1 93 16 V IRQ11 CC 92 17 MA7 IRQ12 91 18 Am79C930 MA6 RFRSH 90 19 MA5 V CC 89 20 VSSM TDI 88 21 MA4 TRST 87 22 MA3 TMS 86 23 MA2 TDO 85 24 MA1 TCK 84 25 MA0 PMX1 26 83 MD0 PMX2 27 82 MD1 TES
ページ1に含まれる内容の要旨
PRELIMINARY
Am79C930
PCnet™-Mobile
Single-Chip Wireless LAN Media Access Controller
DISTINCTIVE CHARACTERISTICS
n Capable of supporting the IEEE 802.11 standard parameters, and ISA Plug and Play
(draft) configuration parameters
n Supports the Xircom Netwave™ media access n Provides integrated Transceiver Attachment
control (MAC) protocols Interface (TAI), supporting Frequency-Hopping
Spread Spectrum, Direct Sequence Spread
n Supports MAC layer functio
ページ2に含まれる内容の要旨
PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C930 V C \W OPTIONAL PROCESSING \W = Trimmed and Formed in a Tray OPERATING CONDITIONS C = Commercial (0 C to +70 C) PACKAGE TYPE V = 144-Pin Thin Quad Flat Pack (PQT144) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C930 Single-Chip Wireless LAN Media Access Co
ページ3に含まれる内容の要旨
PRELIMINARY BLOCK DIAGRAM PCMCIA Mode TRST JTAG TMS/T3 Control MOE TDI/T1 Block TDO/T2 MWE MA 16–0 MD 7–0 RXCIN ANTSLT XCE ANTSLT SAR6–0 SCE ADIN2–1 FCE ADREF RXDATA RXC USER6–0 SDCLK A14–0 SDDATA Transceiver D7–0 SDSEL3–1 Attachment CA16–8 REG Interface TXCMD CE1 CAD 7–0 DRQ0 TXCMD OE TXMOD INT1 DRQ1 Bus MAC TXDATA IORD Interface ALE INT0 Control TXDATA Unit Unit IOWR (PCMCIA) (80188 core) RXPE RESET WR TXPE WE HFPE SRDY WAIT HFCLK INPACK LFPE UCS IREQ LFCLK LCS STSCHG FDET LNK PMX2–1 RESET
ページ4に含まれる内容の要旨
PRELIMINARY BLOCK DIAGRAM Bus Interface Unit MD[7:0] MA[16:0] System IREQ Interrupt CA16 Generator Latch ALE A14–0 or LA23–17, SA16–0 CA15–8 Address Buffer Bus Multi- D7–0 CAD7–0 Data Buffer plexer MIR0 SIR0 MIR1 SIR1 ... ... MIR15 SIR7 MOE Slave PCMCIA Control MWE PCMCIA Slave or and ISA ISA Control Signals Control UCS Memory and and I/O Arbitration LCS for SRDY Memory PCMCIA Interface Config Registers XCE Bus FCE Plug and Play Control Module TAICE SCE 80188 IS
ページ5に含まれる内容の要旨
PRELIMINARY BLOCK DIAGRAM Transceiver Attachment Interface Unit Transceiver IRQ Control Interrupt Transceiver Interface Signals Generator Unit Control MD[7:0] TIR0 TCR0 TX TIR... TCR... RX FIFO FIFO TIR31 TCR31 8 15 Bytes Bytes P->S S->P MUX TAICE Slave C Slave Control R Control Memory C Interface MA[4:0] C Bus I/O R DRQ[1:0] and DMA C FDET SFD Detect RXCSEL Count RXCIN M MUX C U DPLL Phylen X RXD ÷80 BIAS TXD Suppress ÷40 M ÷5 U TXC Sleep X ÷10 RESET ÷20 RXC CLKIN
ページ6に含まれる内容の要旨
AMD P R E L I M I N A R Y TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 BLOCK DIAGRAM .
ページ7に含まれる内容の要旨
AMD P R E L I M I N A R Y Pin 3: USER4/LA17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin 45: STSCHG/BALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin 90: USER0/RFRSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin 91: USER1/IRQ12/EXTCTS/EXINT188 . . . . . . . . . .
ページ8に含まれる内容の要旨
AMD P R E L I M I N A R Y Bus Interface Unit Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Transceiver Attachment Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TX Power Ramp Control . . . . . . . . . . . . . . . . . . . .
ページ9に含まれる内容の要旨
AMD P R E L I M I N A R Y LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SWRESET (SIR0[7]) . . . .
ページ10に含まれる内容の要旨
AMD P R E L I M I N A R Y TIR10: TX FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TIR11: Transmit Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TIR12: Byte Count Register LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TIR13: Byte Count Register MSB . . . . . . . . . . . .
ページ11に含まれる内容の要旨
AMD P R E L I M I N A R Y TCR24: RSSI Sample Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 TCR25: RSSI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 TCR26: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TCR27: TIP LED Scramble . . . . . . . . . . .
