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Preliminary User’s Manual
µµ PD98502
µµ
Network Controller
Document No. S15543EJ1V0UM00 (1st edition)
Date Published December 2001 NS CP(K)
2001
Printed in Japan
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[MEMO] 2 Preliminary User’s Manual S15543EJ1V0UM
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SUMMARY OF CONTENTS CHAPTER 1 INTRODUCTION ..................................................................................................................23 CHAPTER 2 VR4120A ...............................................................................................................................57 CHAPTER 3 SYSTEM CONTROLLER ...................................................................................................185 CHAPTER 4 ATM CELL PROCESSOR.............................
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build stati
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VR4100, VR4102, VR4111, VR4120A, VR4300, VR4305, VR4310, VR4400, VR5000, VR10000, VR Series, VR4000 Series, VR4100 Series, and EEPROM are trademarks of NEC Corporation. Micro Wire is a trademark of National Semiconductor Corp. iAPX is a trademark of Intel Corp. DEC VAX is a trademark of Digital Equipment Corp. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company, Ltd. Ethernet is a trademark of Xerox Corp. MIPS is a trademark of MIP
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PREFACE Readers This manual is intended for engineers who need to be familiar with the capability of the µ PD98502 in order to develop application systems based on it. Purpose The purpose of this manual is to help users understand the hardware capabilities (listed below) of the µ PD98502. Configuration This manual consists of the following chapters: • Introduction • VR4120A CPU • System controller • ATM cell processor • Ethernet controller • USB controller • PCI controller • UART • Timer • Mic
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CONTENTS CHAPTER 1 INTRODUCTION ...............................................................................................................23 1.1 Features......................................................................................................................................23 1.2 Ordering Information.................................................................................................................23 1.3 System Configuration........................................
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2.1.6 Floating-point unit (FPU)................................................................................................................64 2.1.7 CPU core memory management system (MMU) ...........................................................................65 2.1.8 Translation lookaside buffer (TLB).................................................................................................65 2.1.9 Operating modes.....................................................................
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CHAPTER 3 SYSTEM CONTROLLER...............................................................................................185 3.1 Overview...................................................................................................................................185 3.1.1 CPU interface..............................................................................................................................185 3.1.2 Memory interface......................................................
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3.4.15 SDRAM refresh............................................................................................................................219 3.4.16 Memory-to-CPU prefetch FIFO....................................................................................................219 3.4.17 CPU-to-memory write FIFO .........................................................................................................219 3.4.18 SDRAM memory initialization ......................................
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4.4.18 A_T1R (T1 Time Register)...........................................................................................................245 4.4.19 A_TSR (Time Stamp Register) ....................................................................................................245 4.4.20 A_IBBAR (IBUS Base Address Register) ....................................................................................245 4.4.21 A_INBAR (Instruction Base Address Register).....................................
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5.2.20 En_HT1 (Hash Table Register 1).................................................................................................290 5.2.21 En_HT2 (Hash Table Register 2).................................................................................................290 5.2.22 En_CAR1 (Carry Register 1) .......................................................................................................291 5.2.23 En_CAR2 (Carry Register 2) .................................................
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6.2.20 U_RP1IR (USB Rx Pool1 Information Register) ..........................................................................327 6.2.21 U_RP1AR (USB Rx Pool1 Address Register) .............................................................................327 6.2.22 U_RP2IR (USB Rx Pool2 Information Register) ..........................................................................328 6.2.23 U_RP2AR (USB Rx Pool2 Address Register) ...................................................................
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CHAPTER 7 PCI CONTROLLER.........................................................................................................370 7.1 Overview...................................................................................................................................370 7.2 Bus Bridge Functions..............................................................................................................371 7.2.1 Internal bus to PCI transaction............................................
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8.3.4 UARTIER (UART Interrupt Enable Register)...............................................................................416 8.3.5 UARTDLL (UART Divisor Latch LSB Register) ...........................................................................416 8.3.6 UARTDLM (UART Divisor Latch MSB Register) .........................................................................417 8.3.7 UARTIIR (UART Interrupt ID Register).............................................................................
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LIST OF FIGURES (1/5) Figure No. Title Page 1-1 Examples of the µ PD98502 System Configuration ........................................................................................24 1-2 Block Diagram of the µ PD98502....................................................................................................................25 1-3 Block Diagram of VR4120A RISC Processor..................................................................................................26 1-4 Block Diag
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LIST OF FIGURES (2/5) Figure No. Title Page 2-29 Supervisor Mode Address Space ................................................................................................................108 2-30 Kernel Mode Address Space .......................................................................................................................111 2-31 µ PD98502 Physical Address Space ............................................................................................................11
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LIST OF FIGURES (3/5) Figure No. Title Page 2-71 Instruction Cache State Diagram .................................................................................................................173 2-72 Data Check Flow on Instruction Fetch .........................................................................................................174 2-73 Data Check Flow on Load Operations .........................................................................................................174
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LIST OF FIGURES (4/5) Figure No. Title Page 4-19 Open_Channel Command and Indication....................................................................................................258 4-20 Close_Channel Command and Indication ...................................................................................................259 4-21 Tx_Ready Command and Indication............................................................................................................260 4-22 Add_Buffers
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LIST OF FIGURES (5/5) Figure No. Title Page 6-16 Data Receiving in EndPoint0, EndPoint6.....................................................................................................349 6-17 EndPoint2, EndPoint4 Receive Normal Mode..............................................................................................349 6-18 EndPoint2, EndPoint4 Receive Assemble Mode .........................................................................................350 6-19 EndPoint2, EndPo
