ページ1に含まれる内容の要旨
AN93
Si2493/57/34/15/04 (Revision D) and Si2494/39
Modem Designer’s Guide
1. Introduction
The Si2494/93/57/39/34/15/04 ISOmodem chipset family consists of a 38-pin QFN (Si2494/39) or 24-pin TSSOP
(Si2493/57/34/15/04) or 16-pin SOIC (Si2493/57/34/15/04) low-voltage modem device, and a 16-pin SOIC line-
side DAA device (Si3018/10) connecting directly with the telephone local loop (Tip and Ring). This modem solution
is a complete hardware (controller-based) modem that connects to a host processor
ページ2に含まれる内容の要旨
AN93 2 Rev. 1.3
ページ3に含まれる内容の要旨
AN93 TABLE OF CONTENTS Section Page 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. Modem (System-Side) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1. Resetting the Device . . . . . . . . . . . . . . . . . .
ページ4に含まれる内容の要旨
AN93 2.6.6.2. AT Command Macro Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.6.3. Autoloading Firmware Upgrade Example . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.6.4. Combination Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3. DAA (Line-Side) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1. Hookswitch and DC Termination . . . . . . . . .
ページ5に含まれる内容の要旨
AN93 5.7.11. U4F (Flash Hook Time Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.7.12. U50–U51 (Loop Current Debouncing Registers) . . . . . . . . . . . . . . . . . . . . . 105 5.7.13. U52 (Transmit Level Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.7.14. U53 (Modem Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.7.15. U54 (Calibration Timing Register) . . . . . . . . . . . . .
ページ6に含まれる内容の要旨
AN93 6.6. Intrusion/Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.6.1. On-Hook Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.6.1.1. Line Not Present/In Use Indication (Method 1—Fixed) . . . . . . . . . . . . . 161 6.6.1.2. Line Not Present/In Use Indication (Method 2—Adaptive). . . . . . . . . . . 162 6.6.2. Off-Hook Condition. . . . . . . . . . . . . . . . . . . . . . . . . .
ページ7に含まれる内容の要旨
AN93 7.5.8. Speakerphone Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.6. Telephone Answering Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.6.1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.6.2. TAM Hands-Free—Idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.6.2.1. Record OGM . .
ページ8に含まれる内容の要旨
AN93 9. Chinese ePOS SMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 9.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 9.2. SMS AT Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 9.2.1. SMS User Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ9に含まれる内容の要旨
AN93 1.1. Selection Guide Tables 1 through 3 list the modulations, protocols, carriers, tones and interface modes supported by the Si2494/39 and Si2493/57/34/15/04 ISOmodem family. The Si2493 supports all modulations and protocols from Bell 103 through V.92. The Si2457 supports all modulations and protocols from Bell 103 through V.90. The Si2434 supports all modulations and protocols from Bell 103 through V.34. The Si2415 supports all modulations and protocols from Bell 103 through V.32bis. The
ページ10に含まれる内容の要旨
AN93 Table 3. Carriers and Tones Specification Transmit Carrier Receive Carrier Answer Carrier Detect (Acquire/ (Hz) (Hz) Tone (Hz) Release) V.92 Variable Variable per ITU-T V.92 V.90 Variable Variable per ITU-T V.90 V.34 Variable Variable per ITU-T V.34 V.32bis 1800 1800 2100 per ITU-T V.32bis V.32 1800 1800 2100 per ITU-T V.32 V.29 1700 1700 per ITU-T V.29 V.22bis, V.22 1200 2400 2100 –43 dBm/–48 dBm Originate/answer 2400 1200 –43 dBm/–48 dBm V.21 1180/980 1850/1650 2100 –43 dBm/–48 dBm Origin
ページ11に含まれる内容の要旨
AN93 2. Modem (System-Side) Device The Si24xx ISOmodem system-side devices contain a controller, a DSP, program memory (ROM), data memory (RAM), UART, SPI and parallel interfaces, a crystal oscillator, and an isolation capacitor interface. The following sections describe the reset sequence, the host interface, the isolation interface, low-power modes, SSI/voice mode and the EEPROM interface. 2.1. Resetting the Device Reset is required after power-on or brownout conditions (the supply dropping
ページ12に含まれる内容の要旨
AN93 6. Set non-default frequency values—Ring. 7. Set non-default filter parameters. 8. Set non-default S-register values. The modem is now ready to detect rings, answer another modem, call, or dial out to a remote modem. Some key default settings for the modem after reset or powerup include the following: V.92 and fall-backs enabled (Si2494/93) V.90 and fall-backs enabled (Si2457) V.34 and fall-backs enabled (Si2439/34) V.32bis and fall-backs enabled (Si2415) V.22bis and fall-backs en
ページ13に含まれる内容の要旨
AN93 2.1.3. Reset-Strap Options for 16-Pin SOIC Package The clock frequency and interface on the 16-pin SOIC package are selected according to Table 5 below. The parallel interface, EEPROM and autobaud options are not available in the 16-pin SOIC package. Table 5. SOIC-16 Reset-Strap Options Mode Reset-Strap Pins Interface Input Clock Pin 3 Pin 5, RXD/MISO Pin 7, CTS/SCLK Pin 11 Pin 15 RI INT DCD UART 32 kHz 0 X 1 1 X 4.9152 MHz 1 X 1 1 1 27 MHz 1 X 1 1 0 SPI 32 kHz 1 1 X 0 1 4.9152 MHz 0 1 X 0
ページ14に含まれる内容の要旨
AN93 2.1.4.1. Reset Strapping Options for TSSOP-24 with UART-Interface UART-interface options for the 24-pin TSSOP package are shown in Table 6 below. Table 6. TSSOP-24 UART-Interface Options Mode Reset-Strap Pins Input Clock Autobaud Three-Wire Pin 4 Pin 11, CTS Pin 17 Pin 18 Pin 23 Disabled? EEPROM FSYNC Pin 15, AOUT RI SDI/EESD DCD Interface? Pin 16, INT 32 kHz No No 1 1 0 1 X Yes 0 1 0 1 X Yes No 1 1 0 0 X Yes 0 1 0 0 X 4.9152 MHz No No 1 1 1 1 1 Yes 0 1 1 1 1 Yes No 1 1 1 0 1 Yes 0 1 1 0 1
ページ15に含まれる内容の要旨
AN93 2.1.4.3. Reset Strapping Options for TSSOP with SPI-Interface Table 8 lists the SPI-interface options for the 24-pin TSSOP package. Table 8. TSSOP-24 SPI-Interface Clock-Frequency Options Mode Reset-Strap Pins Input Clock Three-Wire Pin 4 Pin 9, RXD Pin 16 Pin 17 Pin 23 EEPROM FSYNC Pin 11, SCLK INT RI DCD Interface? Pin 15, AOUT Pin 18, SDI/EESD 32 kHz No 1 1 0 1 1 Yes 0 1 0 1 1 4.9152 MHz No 1 1 0 0 X Yes 0 1 0 0 X 27 MHz No 1 1 0 1 0 Yes 0 1 0 1 0 2.1.5. Reset Strapping Options for QFN
ページ16に含まれる内容の要旨
AN93 2.1.5.2. Reset Strapping Options for QFN Parts with SPI Operation Table 10 lists the reset strapping options for QFN parts with SPI operation. Table 10. Reset Strapping Options for QFN parts with SPI Operation Input Clk Three-Wire FSYNCH AOUT EECLK INT RI SDI DCD MISO EEPROM Interface Pin 2 Pin 15 Pin 13 Pin 35 Pin 19 Pin 8 Pin 28 Pin 22 32 kHz No 1 1 1 0 1 1 1 1 Yes 0 1 1 0 1 1 1 1 4.9152 MHz No 1 1 1 0 0 1 X 1 Yes 0 1 1 0 0 1 X 1 27 MHz No 1 1 1 0 1 1 0 1 Yes 0 1 1 0 1 1 0 1 2.1.5.3. R
ページ17に含まれる内容の要旨
AN93 2.2. System Interface The ISOmodem can be connected to a host processor through a UART, SPI or parallel interface. Connection to the chip requires low-voltage CMOS signal levels from the host and any other circuitry interfacing directly. The following sections describe the digital interface options in detail. 2.2.1. Interface Selection The interface is selected during reset, as described in "2.1. Resetting the Device". Tables 12, 13, and 14 show the functions of the affected pins for possi
ページ18に含まれる内容の要旨
AN93 Table 14. Pin Functions vs. Interface Mode (QFN-38) Pin # UART Mode SPI Mode Parallel Mode 35 INT INT INT 34 GPIO18 GPIO18 D0 33 GPIO17 GPIO17 D1 32 GPIO16 GPIO16 D2 31 GPIO23 GPIO23 D3 30 GPIO24 GPIO24 D4 29 ESC D5 28 DCD D6 24 RTS SS D7 23 TXD MOSI WR 22 RXD MISO RD 21 CTS SCLK CS 20 GPIO11 GPIO11 A0 19 RI 18 Rev. 1.3
ページ19に含まれる内容の要旨
AN93 2.2.2. Interface Signal Description The following tables describe each set of UART, parallel and SPI interface signals: Table 15. UART-Interface Signals Signal Direction Description TXD Input Data input from host TXD pin RXD Output Data output to host RXD pin RTS Input Active-low request-to-send input for flow control CTS Output Clear to send: Si2493 is ready to receive data on the TXD pin (active low) Table 16. SPI-Interface Signals Signal Direction Description SCLK Input Serial data c
ページ20に含まれる内容の要旨
AN93 The UART interface synchronizes on the start bits of incoming characters and samples the data bit field and stop bits. The interface is designed to accommodate character lengths of 8, 9, 10, and 11 bits giving data fields of 6, 7, 8, or 9 bits. Data width can be set to 6, 7, or 8 bits with the AT\Bn command. Parity can be set to odd, even, mark, or space by the AT\Pn command in conjunction with AT\B2 or AT\B5. Other AT\Bn settings have no parity. Table 18. DTE Rates Ideal DTE Rate (bps) Act
