ページ1に含まれる内容の要旨
Active Receive Mixer
LF to 500 MHz
AD8342
FEATURES FUNCTIONAL BLOCK DIAGRAM
Broadband RF port: LF to 500 MHz VPDC PWDN EXRB COMM
9
Conversion gain: 3.7 dB 12 11 10
Noise figure: 12.2 dB
COMM 8 COMM
13 BIAS
Input IP3: 22.7 dBm
RFCM 14 7 IFOP
Input P1dB: 8.3 dBm AD8342
LO drive: 0 dBm RFIN
15 6 IFOM
Differential high impedance RF input port
VPMX 16 5 COMM
Single-ended, 50 Ω LO input port
3 4
1 2
Single-supply operation: 5 V @ 98 mA
VPLO LOCM LOIN COMM
Power-down mode
Exposed paddl
ページ2に含まれる内容の要旨
AD8342 TABLE OF CONTENTS Specifications..................................................................................... 3 AC Interfaces................................................................................... 15 AC Performance ............................................................................... 4 IF Port .......................................................................................... 16 Spur Table .........................................................
ページ3に含まれる内容の要旨
AD8342 SPECIFICATIONS VS = 5 V, TA = 25°C, fRF = 238 MHz, fLO = 286 MHz, LO power = 0 dBm, ZO = 50 Ω, R BIAS = 1.82 kΩ, RF termination = 100 Ω, IF termi- nated into 100 Ω through a 2:1 ratio balun, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit RF INPUT INTERFACE Return Loss Hi-Z input terminated with 100 Ω off-chip resistor 10 dB Input Impedance Frequency = 238 MHz (measured at RFIN with RFCM ac- 1||0.4 kΩ||pF grounded) DC Bias Level Intern
ページ4に含まれる内容の要旨
AD8342 AC PERFORMANCE VS = 5 V, TA = 25°C, LO power = 0 dBm, ZO = 50 Ω, R BIAS = 1.82 kΩ, RF termination 100 Ω, IF terminated into 100 Ω via a 2:1 ratio balun, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit 1 RF FREQUENCY RANGE 50 500 MHz 1 LO FREQUENCY RANGE High side LO 60 850 MHz 1 IF FREQUENCY RANGE 10 350 MHz CONVERSION GAIN f = 460 MHz, f = 550 MHz, f = 90 MHz 3.2 dB RF LO IF fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz 3.7 dB SS
ページ5に含まれる内容の要旨
AD8342 SPUR TABLE VS = 5 V, TA = 25°C, RF and LO power = 0 dBm, fRF = 238MHz, fLO = 286MHz, ZO = 50 Ω, R BIAS = 1.82 kΩ, RF termination 100 Ω, IF terminated into 100 Ω via a 2:1 ratio balun. Note: Measured using standard test board. Typical noise floor of measurement system = −100 dBm. Table 3. m nfRF − mfLO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 <−100 −25 −54 −28 −45 −35 −39 −36 −42 −57 −44 −42 −41 −46 −59 1 −39 3.5 −42 −6 −48 −16 −50 −28 −57 −37 −68 −45 −54 −37 −61 2 −52 −47 −51 −4
ページ6に含まれる内容の要旨
AD8342 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage, V 5.5 V S rating only; functional operation of the device at these or any RF Input Level 12 dBm other conditions above those indicated in the operational sec- LO Input Level 12 dBm tion of this specification is not implied. Exposure to absolute PWDN Pin VS + 0.5 V maximum rating
ページ7に含まれる内容の要旨
AD8342 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR VPLO 1 12 VPDC LOCM 2 11 PWDN AD8342 LOIN 3 10 EXRB TOP VIEW (Not to Scale) COMM 4 9 COMM Figure 2. 16-Lead LFCSP Table 5. Pin Function Descriptions Pin No. Mnemonic Function 1 VPLO Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V. 2 LOCM AC Ground for Limiting LO Amplifier. Internally biased to Vs − 1.6 V. AC-couple to ground. 3 LOIN LO Input. Nominal input level 0 dBm. Input level range −10 dBm t
ページ8に含まれる内容の要旨
AD8342 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, ZO = 50 Ω, R BIAS = 1.82 kΩ, RF termination 100 Ω, IF t erminated into 100 Ω via a 2:1 ratio balun, unless otherwise noted. 6 6 5 5 RF = 238MHz IF = 48MHz 4 4 RF = 460MHz 3 3 IF = 140MHz IF = 10MHz IF = 90MHz 2 2 1 1 50 100 150 200 250 300 350 400 450 500 550 10 50 100 150 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 6. Conversion Gain vs. IF Frequency Figure 3. Conve
ページ9に含まれる内容の要旨
AD8342 27 27 26 26 25 25 IF = 48MHz 24 24 IF = 10MHz IF = 90MHz 23 23 RF = 460MHz 22 22 RF = 238MHz 21 21 IF = 140MHz 20 20 19 19 18 18 17 17 50 100 150 200 250 300 350 400 450 500 550 10 50 100 150 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 9. Input IP3 vs. RF Frequency Figure 12. Input IP3 vs. IF Frequency 27 27 26 26 25 25 IF = 48MHz 24 IF = 10MHz 24 23 23 22 22 21 140MHz 21 IF = 90MHz 20 20 19 19 18 18 17 17 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 4.75 4.80 4.85 4.90 4.9
ページ10に含まれる内容の要旨
AD8342 13 10 12 9 RF = 460MHz 11 8 10MHz 90MHz 10 7 RF = 238MHz 9 6 8 5 48MHz 7 4 140MHz 6 3 5 2 4 1 3 0 50 100 150 200 250 300 350 400 450 500 550 10 50 100 150 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 15. Input P1dB vs. RF Frequency Figure 18. Input P1dB vs. IF Frequency 10.0 10 9.5 9 9.0 IF = 10MHz 8 IF = 90MHz 8.5 7 8.0 6 IF = 140MHz 7.5 5 IF = 48MHz 7.0 4 6.5 3 6.0 2 5.5 1 5.0 0 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 4.75 4.85 4.95 5.05 5.15 5.25 LO LEVEL (dBm) VPOS
ページ11に含まれる内容の要旨
AD8342 60 60 IF = 90MHz IF = 10MHz RF = 238MHz RF = 460MHz IF = 140MHz 50 50 40 40 IF = 48MHz 30 30 20 20 10 10 0 0 100 150 200 250 300 350 400 450 500 550 10 50 100 150 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 21. Input IP2 vs. RF Frequency (Second RF = R F - 50 MHz) Figure 24. Input IP2 vs. IF Frequency (Second RF = R F - 50 MHz) 60 60 58 58 IF = 10MHz 56 56 IF = 48MHz 54 54 52 52 50 50 48 48 IF = 90MHz 46 46 IF = 140MHz 44 44 42 42 40 40 –15 –13 –11 –9 –7 –5 –3 –
ページ12に含まれる内容の要旨
AD8342 16 30 NORMAL MEAN = 12.25 STD. DEV. = 0.14 15 25 NF PERCENTAGE 14 20 NF = 140MHz NF = 90MHz 13 15 12 10 NF = 10MHz NF = 48MHz 11 5 10 0 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 11.8 11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 LO POWER (dBm) NOISE FIGURE (dB) Figure 27. Noise Figure vs. LO Power, f = 238 MHz Figure 30. Noise Figure Distribution, f = 238 MHz, f = 286 MHz RF RF LO 30 105 5.0 4.5 25 100 4.0 INPUT IP3 3.5 20 95 3.0 2.5 15 90 2.0 NOISE FIGURE 10 85 1.5 CURRENT 1.0 5 80
ページ13に含まれる内容の要旨
AD8342 0 120 –10 100 –20 –30 80 –40 60 –50 –60 40 –70 20 –80 –90 0 50 250 450 650 850 –40 –20 0 20 40 60 80 LO FREQUENCY (MHz) TEMPERATURE ( °C) Figure 33. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm Figure 36. Supply Current vs. Temperature 0 0 –5 –2 –10 –4 –15 –6 –20 –8 IF = 10MHz –25 –10 –30 –12 –35 –14 –40 –16 IF = 48MHz –45 –18 50 100 150 200 250 300 350 400 450 500 550 60 160 260 360 460 560 660 760 860 RF FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 34. RF to IF Feedthr
ページ14に含まれる内容の要旨
AD8342 CIRCUIT DESCRIPTION EXTERNAL The AD8342 is an active mixer optimized for operation within BIAS VPDC RESISTOR PWDN the input frequency range of near dc to 500 MHz. It has a dif- ferential, high impedance RF input that can be terminated or BIAS matched externally. The RF input can be driven either single- ended or differentially. The LO input is a single-ended 50 Ω RFIN IFOP V TO input. The IF outputs are differential open-collectors. The mixer I IFOM RFCM current can be adjusted by
ページ15に含まれる内容の要旨
AD8342 AC INTERFACES The AD8342 is designed to downconvert radio frequencies (RF) Table 4. Dynamic Performance for Various Input Networks to lower intermediate frequencies (IF) using a high or low-side Input 50 Ω 100 Ω 500 Ω Matched local oscillator (LO). The LO is injected into the mixer core at a Network Shunt Shunt Shunt (Fig. 40) frequency higher or lower than the desired input RF. The Gain (dB) 0.66 3.5 5.3 9.3 difference between the LO and the RF , f − f (high side) or LO RF, I
ページ16に含まれる内容の要旨
AD8342 IF PORT The high input impedance of the AD8351 allows for a shunt differential termination to provide the desired 100 Ω lo ad to the The IF port comprises open-collector differential outputs. The AD8342 IF output port. NPN open collectors can be modeled as current sources that are shunted with resistances of ~10 kΩ in p arallel with capacitances It is necessary to bias the open-collector outputs using one of of ~1 pF. the schemes presented in Figure 47 and Figure 48. Figure
ページ17に含まれる内容の要旨
AD8342 +V 30 S AD8342 MODELED 25 COMM 8 2:1 IF OUT Z = 50 Ω IFOP 7 O 20 IFOM 6 MEASURED 15 COMM 5 Z = 100 Ω L Figure 47. Biasing the IF Port Open-Collector Outputs 10 Using a Center-Tapped Impedance Transformer +V 5 S AD8342 0 COMM 8 RFC 10 100 1000 IF OUT+ IF LOAD ( Ω) IFOP 7 IMPEDANCE Z = 100 Ω TRANSFORMING Z L L NETWORK IFOM 6 Figure 49. Voltage Conversion Gain vs. IF Loading IF OUT– RFC COMM 5 LO CONSIDERATIONS The LOIN port provides a 50 Ω load impedance with common- +V S mode d
ページ18に含まれる内容の要旨
AD8342 HIGH IF APPLICATIONS production concerns due to the sensitivity of the match. For In some applications it may be desirable to use the AD8342 as this application, it is advantageous to shunt down the ~1 kΩ an up-converting mixer. The AD8342 is a broadband mixer input impedance using an external shunt termination resistor capable of both up and down conversion. Unlike other mixers to allow for a lower Q reactive matching network. The input is that rely on on-chip reactive circu
ページ19に含まれる内容の要旨
AD8342 EVALUATION BOARD An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a balun transformer. The schematic for the evaluation board is presented in Figure 53. R8 PWDN PWDN C11 10k Ω 100pF W1 R6 R9 GND VPOS R7 0 Ω VPOS 1.82k Ω 0 Ω C12 C13 0.1 µF 100pF 12 11 10 9 VPDC PWDN EXRB COMM Z2 OPEN R3 OPEN R10 13 COMM COMM 8 0 Ω IF_OUT+ C1 T1 L1 1000pF Z1 50 Ω 34 0 Ω OPEN TRACE 14 7 RFCM IFOP R12 100 Ω TRACES, 2
ページ20に含まれる内容の要旨
AD8342 Preliminary Technical Data OUTLINE DIMENSIONS 0.50 0.40 0.30 3.00 0.60 MAX BSC SQ * 1.65 13 16 0.45 1 12 1.50 SQ PIN 1 1.35 2.75 TOP EXPOSED INDICATOR BSC SQ VIEW PAD (BOTTOM VIEW) 9 4 8 5 0.50 BSC 0.25 MIN 1.50 REF 0.80 MAX 12° MAX 0.65 TYP 0.90 0.85 0.05 MAX 0.80 0.02 NOM SEATING 0.30 PLANE 0.20 REF 0.23 0.18 * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad
