ページ1に含まれる内容の要旨
Complete 10-Bit 20 MSPS
a
CCD Signal Processor
AD9843A
FEATURES PRODUCT DESCRIPTION
20 MSPS Correlated Double Sampler (CDS) The AD9843A is a complete analog signal processor for CCD
4 dB 6 dB Variable CDS Gain with 6-Bit Resolution applications. It features a 20 MHz single-channel architecture
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) designed to sample and condition the outputs of interlaced and
Low Noise Clamp Circuits progressive scan area CCD arrays. The AD9843A’s signal chain
Ana
ページ2に含まれる内容の要旨
AD9843A–SPECIFICATIONS (T to T , AVDD = DVDD = 3.0 V, f = 20 MHz, unless otherwise noted.) GENERAL SPECIFICATIONS MIN MAX DATACLK Parameter Min Typ Max Unit TEMPERATURE RANGE Operating –20 +85 °C Storage –65 +150 °C POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver 2.7 3.6 V POWER CONSUMPTION Normal Operation (Specified Under Each Mode of Operation) Power-Down Modes Fast Recovery Mode 45 mW Standby 5 mW Total Power-Down 1 mW MAXIMUM CLOCK RATE 20 MHz A/D CONVERTER Resolution 10 Bits Different
ページ3に含まれる内容の要旨
AD9843A (T to T , AVDD = DVDD = 3.0 V, f = f = f = 20 MHz, unless otherwise noted.) CCD-MODE SPECIFICATIONS MIN MAX DATACLK SHP SHD Parameter Min Typ Max Unit Notes POWER CONSUMPTION 78 mW See TPC 1 for Power Curves MAXIMUM CLOCK RATE 20 MHz CDS 1 Allowable CCD Reset Transient 500 mV See Input Waveform in Note 1 1 Max CCD Black Pixel Amplitude 200 mV 1 Max Input Range Before Saturation 1.0 V p-p With 4 dB CDS Gain Max Input Range Before Saturation 1.5 V p-p With –2 dB CDS Gain Max Input Range Be
ページ4に含まれる内容の要旨
AD9843A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS (T to T , AVDD = DVDD = 3.0 V, f = 20 MHz, unless otherwise noted.) MIN MAX DATACLK Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER Gain 0dB Max Input Range 1.0 V p-p VGA Max Output Range 2.0 V p-p Gain Control Resolution 1023 Steps Gain (Selected Using VGA Gain Register) Min Gain 0 dB Max Gain 36 dB Specifications subject to change without notice. (T to T , AVDD = DVDD = 3.0 V, f = 20 MHz, unless otherwise
ページ5に含まれる内容の要旨
AD9843A (C = 20 pF, f = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. L SAMP TIMING SPECIFICATIONS Serial Timing in Figures 8–10.) Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period t 48 50 ns CONV DATACLK High/Low Pulsewidth t 20 25 ns ADC SHP Pulsewidth t 712.5 ns SHP SHD Pulsewidth t 712.5 ns SHD CLPDM Pulsewidth t 4 10 Pixels CDM 1 CLPOB Pulsewidth t 2 20 Pixels COB SHP Rising Edge to SHD Falling Edge t 012.5 ns S1 SHP Rising Edge to SHD
ページ6に含まれる内容の要旨
AD9843A PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 DRVSS 1 36 AUX1IN PIN 1 DRVSS 2 IDENTIFIER 35 AVSS 3 (LSB) D0 34 AUX2IN 4 D1 33 AVDD2 5 D2 32 BYP4 AD9843A D3 6 31 NC TOP VIEW D4 7 30 CCDIN (Not to Scale) D5 8 29 BYP2 9 D6 28 BYP1 10 D7 27 AVDD1 11 D8 26 AVSS 12 (MSB) D9 25 AVSS 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin Number Name Type Description 1, 2 DRVSS P Digital Driver Ground 3–12 D0–D9 DO Digital Data Outputs 13 DRVDD P Digital Output
ページ7に含まれる内容の要旨
AD9843A DEFINITIONS OF SPECIFICATIONS chain at the specified gain setting. The output noise can be DIFFERENTIAL NONLINEARITY (DNL) converted to an equivalent voltage, using the relationship 1 LSB N An ideal ADC exhibits code transitions that are exactly 1 LSB = (ADC Full Scale/2 codes) when N is the bit resolution of the apart. DNL is the deviation from this ideal value. Thus every code ADC. For the AD9843A, 1 LSB is 2 mV. must have a finite width. No missing codes guaranteed to 10-bit resoluti
ページ8に含まれる内容の要旨
AD9843A–Typical Performance Characteristics 4 100 90 3 V = 3.3V DD 80 V = 3.0V DD 70 2 V = 2.7V DD 60 1 50 0 40 0 400 52 10 150 200 600 800 1000 VGA GAIN CODE – LSB SAMPLE RATE – MHz TPC 1. Power vs. Sample Rate TPC 3. Output Noise vs. VGA Gain 0.5 0.25 0 –0.25 –0.5 0 200 400 600 800 1000 TPC 2. Typical DNL Performance REV. 0 –8– POWER DISSIPATION – mW OUTPUT NOISE – LSB
ページ9に含まれる内容の要旨
AD9843A CCD-MODE AND AUX-MODE TIMING CCD SIGNAL N N+1 N+2 N+9 N+10 t ID t ID SHP t t t S1 CP S2 SHD t INH DATACLK t OD t H OUTPUT N–10 N–9N–8N–1N DATA NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 5. CCD-Mode Timing HORIZONTAL BLANKING EFFECTIVE PIXELS OPTICAL BLACK PIXELS DUMMY PIXELS EFFECTIVE PIXELS CCD SIGNAL CLPOB CLPDM PBLK OUTPUT EFFECTIVE PIXEL DATA OB PIXEL
ページ10に含まれる内容の要旨
AD9843A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map Register Address Data Bits Name A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Operation 0 0 0 Channel Select Power-Down Software OB Clamp 0* 1** 0* 0* 0* CCD/AUX Modes Reset On/Off VGA Gain 1 0 0 LSB MSB X Clamp Level 0 1 0 LSB MSB X X X Control 1 1 0 0* 0* 0* CDS Gain Clock Polarity Select for 0* 0* Three- X On/Off SHP/SHD/CLP/DATA State CDS Gain 0 0 1 LSB MSB X X X X X *Internal use
ページ11に含まれる内容の要旨
AD9843A Table II. Operation Register Contents (Default Value x000) Optical Black Clamp Reset Power-Down Modes Channel Selection D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 1** 0* 0 Enable Clamping 0 Normal 0 0 Normal Power 0 0 CCD-Mode 1 Disable Clamping 1 Reset All 0 1 Fast Recovery 0 1 AUX1-Mode Registers 1 0 Standby 1 0 AUX2-Mode to Default 1 1 Total Power-Down 1 1 Test Only *Must be set to zero. **Set to one. Table III. VGA Gain Register Contents (Default Value x096) MSB LSB D10 D9 D8 D7 D6
ページ12に含まれる内容の要旨
AD9843A DC RESTORE CDS GAIN REGISTER INTERNAL V 6 REF –2dB TO +10dB 2dB TO 36dB 2V FULL SCALE 0.1F CCDIN 10 10-BIT CDS VGA DOUT ADC INPUT OFFSET CLAMP CLPOB OPTICAL BLACK 8-BIT CLAMP DAC 10 CLPDM DIGITAL 0 TO 64 LSB FILTERING VGA GAIN REGISTER 8 CLAMP LEVEL REGISTER Figure 11. CCD-Mode Block Diagram CIRCUIT DESCRIPTION AND OPERATION Table VII. Example CDS Gain Settings The AD9843A signal processing chain is shown in Figure 11. Recommended Each processing step is essential in achieving a high-qu
ページ13に含まれる内容の要旨
AD9843A together with CLPOB or separately. The CLPDM pulse should AD9843A’s optical black clamping may be disabled using Bit D5 be a minimum of four pixels wide. in the Operation Register (see Serial Interface Timing and Inter- nal Register Description section). When the loop is disabled, Variable Gain Amplifier the Clamp Level Register may still be used to provide pro- The VGA stage provides a gain range of 2 dB to 36 dB, program- grammable offset adjustment. mable with 10-bit resolution throug
ページ14に含まれる内容の要旨
AD9843A 0.4V 0.8V ??V 0dB TO 36dB 5k 0.1F AUX1IN INPUT SIGNAL VGA ADC MIDSCALE 10 0.4V 0.4V VGA GAIN REGISTER Figure 14. AUX1 Circuit Configuration VGA GAIN REGISTER 9 0dB TO 18dB BUFFER AUX2IN VIDEO VGA ADC SIGNAL 0.1F CLAMP LEVEL VIDEO CLAMP CIRCUIT LPF 8 CLAMP LEVEL REGISTER Figure 15. AUX2 Circuit Configuration Table VIII. VGA Gain Register Used for AUX2-Mode MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) X0 XXXXXXXXX0.0 10000000000.0 •• •• •• 111111111118.0 CCD AD9843A DIGITAL OUTPU
ページ15に含まれる内容の要旨
AD9843A APPLICATIONS INFORMATION Grounding and Decoupling Recommendations The AD9843A is a complete Analog Front End (AFE) product As shown in Figure 17, a single ground plane is recommended for digital still camera and camcorder applications. As shown in for the AD9843A. This ground plane should be as continu- Figure 16, the CCD image (pixel) data is buffered and sent to ous as possible, particularly around Pins 25 through 39. This the AD9843A analog input through a series input capacitor. will
ページ16に含まれる内容の要旨
AD9843A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75) 48 37 0.018 (0.45) 36 1 0.276 TOP VIEW (7.00) (PINS DOWN) BSC SQ COPLANARITY 12 25 0.003 (0.08) 0 13 24 MIN 0.019 (0.5) 0.011 (0.27) 0.008 (0.2) BSC 0.006 (0.17) 0.004 (0.09) 0.057 (1.45) 7 0.053 (1.35) 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE REV. 0 –16– PRINTED IN U.S.A. C02194–0–10/00 (rev. 0)
