ページ1に含まれる内容の要旨
Bt8960
Single-Chip 2B1Q Transceiver
The Bt8960 is a full-duplex 2B1Q transceiver based on Rockwell’s HDSL technol-
Distinguishing Features
ogy. It supports Nx64 kbps transmission of more than 18,000 feet over 26 AWG
• Single-chip 2B1Q transceiver solution
copper telephone wire without repeaters. Small size and low power dissipation
• All 2B1Q transceiver functions inte-
make the Bt8960 ideal for line-powered voice pairgain systems capable of provid-
grated into a single monolithic dev
ページ2に含まれる内容の要旨
Ordering Information Order Number Package Ambient Temperature Bt8960EPF 100-Pin Plastic Quad Flat Pack (PQFP) –40˚C to +85˚C Copyright © 1997 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: December 1997 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed fo
ページ3に含まれる内容の要旨
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Figures List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ4に含まれる内容の要旨
Table of Contents Bt8960 Single-Chip 2B1Q Transceiver 2.2.4 Echo Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.4.1 Linear Echo Canceler (LEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.4.2 Nonlinear Echo Canceler (NEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.5 Equal
ページ5に含まれる内容の要旨
Table of Contents Bt8960 Single-Chip 2B1Q Transceiver 3.2.10 0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes) . . . . . . 49 3.2.11 0x0A—Decision Feedback Equalizer Modes Register (dfe_modes) . . . . . . . . . . . 50 3.2.12 0x0B—Transmitter Modes Register (transmitter_modes) . . . . . . . . . . . . . . . . . . 50 3.2.13 0x0C—Timer Restart Register (timer_restart) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.14 0
ページ6に含まれる内容の要旨
Table of Contents Bt8960 Single-Chip 2B1Q Transceiver 3.2.49 0x46, 0x47—Signal Level Meter Register (slm_low, slm_high) . . . . . . . . . . . . . . 65 3.2.50 0x48, 0x49—Far-End Level Meter Register (felm_low, felm_high). . . . . . . . . . . . 65 3.2.51 0x4A, 0x4B—Noise Level Histogram Meter Register (noise_histogram_low, noise_histogram_high) . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.52 0x4C, 0x4D—Bit Error Rate Meter Register (ber_meter_low, ber_meter_high). . . . . . . . . .
ページ7に含まれる内容の要旨
Bt8960 List of Figures Single-Chip 2B1Q Transceiver List of Figures Figure 1-1. 2B1Q Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1-2. Bt8960 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 1-3. PCM6 Voice Pairgain Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 1-4. Pin Diagr
ページ8に含まれる内容の要旨
List of Figures Bt8960 Single-Chip 2B1Q Transceiver viii N8960DSB
ページ9に含まれる内容の要旨
Bt8960 List of Tables Single-Chip 2B1Q Transceiver List of Tables Table 1-1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 1-2. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2-1. Symbol Source Selector/Scrambler Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2-2. Four-Level Bit-to-S
ページ10に含まれる内容の要旨
List of Tables Bt8960 Single-Chip 2B1Q Transceiver x N8960DSB
ページ11に含まれる内容の要旨
1.0 System Overview 1.1 Functional Summary The Bt8960 2B1Q transceiver is an integral component of Rockwell's telecom- munications product line. The major building blocks of a 2B1Q terminal are shown in Figure 1-1. Figure 1-1. 2B1Q Terminal Receive Data Framer/ Bt8960 Transformer Twisted Channel Transceiver and Hybrid Pair Unit Transmit Data N8960DSB 1
ページ12に含まれる内容の要旨
1.0 System Overview Bt8960 1.1 Functional Summary Single-Chip 2B1Q Transceiver The Bt8960 comprises five major functions: a transmit section, a receive sec- tion, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. Figure 1-2 details the connections within and between each of these functional blocks. Figure 1-2. Bt8960 Detailed Block Diagram Receive Section Receive RXP Digital RQ[1]/RDAT Echo Channel Front RXN ADC Equalizer Detector Cancele
ページ13に含まれる内容の要旨
Bt8960 1.0 System Overview 1.1 Functional Summary Single-Chip 2B1Q Transceiver 1.1.1 Transmit Section The source of transmitted symbols is programmable through the microcomputer interface. The primary choices include external 2B1Q-encoded data presented to the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back receive symbols from the detector, or a constant “all ones” source. The symbols are then optionally scrambled. Isolated pulses can also be generated to support t
ページ14に含まれる内容の要旨
1.0 System Overview Bt8960 1.1 Functional Summary Single-Chip 2B1Q Transceiver 1.1.4 Microcomputer Interface The Microcomputer Interface (MCI) provides access to a 256-byte address space within the transceiver. A combination of direct and indirect addressing methods are used to access all internal locations. The MCI is designed to interface with both Intel- and Motorola-style processors with no additional glue logic. A MOTEL control pin is provided to configure the bus interface control/han
ページ15に含まれる内容の要旨
Bt8960 1.0 System Overview 1.2 Applications Single-Chip 2B1Q Transceiver 1.2 Applications 1.2.1 Voice/Data Pairgain A well-established market exists for voice pairgain systems. These systems trans- port several simultaneous phone conversations over a single twisted pair. They are used by telecommunications service providers to maximize the utilization of the existing copper plant, and allow it to provision many more telephone circuits than possible with ordinary 4 kHz analog transport. T
ページ16に含まれる内容の要旨
1.0 System Overview Bt8960 1.2 Applications Single-Chip 2B1Q Transceiver Figure 1-3. PCM6 Voice Pairgain Block Diagram SLIC SLIC SLIC PCM Local Bt8960 Framer Loop SLIC SLIC SLIC 1.2.2 Internet Connectivity Transport The growth of the Internet has created a tremendous demand for additional band- width in the local loop. When existing loop facilities are used to provide connec- tivity to Internet servers, they are limited to the 128 kbps offered by Basic Rate ISDN (BRI) service. Although th
ページ17に含まれる内容の要旨
Bt8960 1.0 System Overview 1.2 Applications Single-Chip 2B1Q Transceiver 1.2.3 ISDN Basic Rate Interface Concentrator Since many telecommunications service providers are positioning BRI service as residential Internet or telecommuter connectivity, the lack of installed copper pairs into the residence could be a serious limitation to the proliferation of the ser- vice. The Bt8960 solves this problem because it is capable of 416 kbps data rates. Thus, it enables the transport of two full BRI
ページ18に含まれる内容の要旨
1.0 System Overview Bt8960 1.3 Pin Descriptions Single-Chip 2B1Q Transceiver 1.3 Pin Descriptions The Bt8960 is packaged in a 100-Pin Plastic Quad Flat Pack (PQFP). The pin assignments are shown in Figure 1-4. A listing of pin labels, numbers, and I/O assignments is given in Table 1-1. Signal definitions are provided in Table 1-2. The coding used in the I/O column is: O = digital output, OA = analog output, OD = open-drain output, I = digital input, IA = analog input, and I/O = bidirectional
ページ19に含まれる内容の要旨
Bt8960 1.0 System Overview 1.3 Pin Descriptions Single-Chip 2B1Q Transceiver Table 1-1. Pin Descriptions Pin Pin Label I/O Pin Pin Label I/O Pin Pin Label I/O Pin Pin Label I/O 1 VDD1 – 26 ADDR[2] I 51 VRXP OA 76 AGND – 2 CS I 27 ADDR[1] I 52 VRXN OA 77 RXP IA 3 RD/DS I 28 ADDR[0] I 53 AGND – 78 RXN IA 4 WR/R/W I 29 SMON O 54 VAA – 79 RXBP IA 5 ALE I 30 VDD1 – 55 VAA – 80 RXBN IA 6 IRQ OD 31 DGND – 56 RBIAS OA 81 VAA – 7 READY OD 32 DGND – 57 VCOMI OA 82 AGND – 8 AD[0] I/O 33 VDD2 – 58 VCOM
ページ20に含まれる内容の要旨
1.0 System Overview Bt8960 1.3 Pin Descriptions Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions (1 of 4) Pin Label Signal Name I/O Definition Microcomputer Interface (MCI) MOTEL Motorola/Intel I Selects between Motorola and Intel handshake conventions for the RD/DS and WR/R/W signals. MOTEL = 1 for Motorola protocol: DS, R/W MOTEL = 0 for Intel protocol: RD, WR ALE Address Latch I Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or Enable ADDR[7:0] w
