ページ1に含まれる内容の要旨
Si4421 Universal ISM Band
Si4421
FSK Transceiver
PIN ASSIGNMENT
DESCRIPTION
Silicon Labs’ Si4421 is a single chip, low power, multi-channel FSK
transceiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 433, 868 and 915 MHz bands.
TM
The Si4421 transceiver is a part of Silicon Labs’ EZRadio product
line, which produces a flexible, low cost, and highly integrated solution
that does not require production alignments. The chip is a comp
ページ2に含まれる内容の要旨
Si4421 Full Baseband Amplifier Transfer Function DETAILED FEATURE-LEVEL DESCRIPTION BW=67kHz The Si4421 FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The Si4421 incorporates a fully integrated multi-band PLL synthesizer,
ページ3に含まれる内容の要旨
Si4421 suggested to turn the output buffer off by the Power Data Validity Blocks Management Command (page 15). RSSI Low Battery Voltage Detector A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given The low battery detector circuit monitors the supply voltage and preprogrammed level. An analog RSSI signal is also available. generates an interrupt if it falls below a programmable threshold The RSSI settling tim
ページ4に含まれる内容の要旨
Si4421 PACKAGE PIN DEFINITIONS Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Pin Name Type Function 1 SDI DI Data input of the serial control interface 2 SCK DI Clock input of the serial control interface 3 nSEL DI Chip select input of the serial control interface (active low) 4 SDO DO Serial data output with bus hold 5 nIRQ DO Interrupt request output (active low) FSK DI Transmit FSK data input (internal pull up resistor 133 k) DATA DO Received
ページ5に含まれる内容の要旨
Si4421 Internal Pin Connections Pin Name Internal connection Pin Name Internal connection VDD 1 SDI 10 nRES 2 SCK PAD 1.5k 3 nSEL VSS 11 VSS 4 SDO 12 RF2 5 nIRQ 13 RF1 FSK 14 VDD 6 DATA nFFS DLCK 15 ARSSI 7 CFIL FFIT VDD nINT 16 8 CLK PAD 10 VDI VSS XTL 9 REF 5
ページ6に含まれる内容の要旨
Si4421 PIN6 Logic Diagram (FSK / DATA / nFFS) PIN10 Logic Diagram (nRES I/O) * Note: These pins can be left floating. 6
ページ7に含まれる内容の要旨
Si4421 Typical Application Typical application with FIFO usage VDD C1 2.2u C3 C2 10n (optional) VDI P7 TP C4 1 16 SDI P6 2.2n (opt.) 2 15 SCK P5 3 14 nSEL P4 4 13 SDO P3 5 Si4421 12 nIRQ P2 (optional)* 6 11 nFFS P1 (optional)* 7 10 FFIT P0 (optional) 8 9 CLK CLKin PCB Antenna nRES (optional) nRESin X1 10MHz Note: * Connections needed only in time critical applications Recommended supply decoupling capacitor values C2 and C3 should be 0603 size ceramic capacitors to achieve the best suppl
ページ8に含まれる内容の要旨
Si4421 GENERAL DEVICE SPECIFICATIONS All voltages are referenced to V , the potential on the ground reference pin VSS. ss Absolute Maximum Ratings (non-operating) Symbol Parameter Min Max Units V Positive supply voltage -0.5 6 V dd V Voltage on any pin (except RF1 and RF2) -0.5 V+0.5 V in dd V Voltage on open collector outputs (RF1, RF2) -0.5 V +1.5 (Note 1) V oc dd I Input current into any pin except VDD and VSS -25 25 mA in ESD Electrostatic discharge with human body model 1000
ページ9に含まれる内容の要旨
Si4421 ELECTRICAL SPECIFICATION o Test Conditions: T = 27 C; V = V = 3.3 V op dd oc DC Characteristics Symbol Parameter Conditions/Notes Min Typ Max Units 433 MHz band 15 Supply current I mA dd_TX_0 868 MHz band 16 (TX mode, P = 0 dBm) out 915 MHz band 17 433 MHz band 22 26 Supply current I mA dd_TX_PMAX 868 MHz band 23 27 (TX mode, P = P ) out max 915 MHz band 24 28 433 MHz band 11 13 I Supply current (RX mode) mA dd_RX 868 MHz band 12 14 915 MHz band 13 15 I
ページ10に含まれる内容の要旨
Si4421 AC Characteristics (PLL parameters) Symbol Parameter Conditions/Notes Min Typ Max Units f PLL reference frequency (Note 2) 9 10 11 MHz ref 433 MHz band, 2.5 kHz resolution 430.24 439.75 Receiver LO/Transmitter carrier f MHz o 868 MHz band, 5.0 kHz resolution 860.48 879.51 frequency 915 MHz band, 7.5 kHz resolution 900.72 929.27 Frequency error < 1kHz t PLL lock time 30 µs lock after 10 MHz step t PLL startup time (Note 10) With a running crystal oscillator 200 300 µ
ページ11に含まれる内容の要旨
Si4421 AC Characteristics (Transmitter) Symbol Parameter Conditions/Notes Min Typ Max Units I Open collector output DC current Programmable 0.5 6 mA OUT Max. output power delivered to 50 In 433 MHz band 7 P dBm max_50 Ohm load over a suitable matching In 868 MHz / 915 MHz bands 5 network (Note 4) In 433 MHz band with monopole antenna 7 Max. EIRP with suitable selected with matching network (Note 4) P dBm max_ant PCB antenna (Note 6) In 868 MHz / 915 MHz bands (Note 5) 7
ページ12に含まれる内容の要旨
Si4421 Note 1: Measured with disabled clock output buffer Note 2: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will change accordingly Note 3: See the BER diagrams in the measurement results section (page 37) for detailed information Note 4: See reference design with 50 Ohm Matching Network (page 39) for details Note 5: See reference design with Resonant PCB Antenna (BIFA) on page 41 for details Note 6: Optimal ant
ページ13に含まれる内容の要旨
Si4421 CONTROL INTERFACE Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16- bit command). Bits having no influence (don’t care) are indicated with X.
ページ14に含まれる内容の要旨
Si4421 Control Commands Control Command Related Parameters/Functions Related control bits Frequency band, crystal oscillator load capacitance, 1 Configuration Setting Command el, ef, b1 to b0, x3 to x0 RX FIFO and TX register enable Receiver/Transmitter mode change, synthesizer, 2 Power Management Command crystal oscillator, PA, wake-up timer, clock output er, ebb, et, es, ex, eb, ew, dc enable 3 Frequency Setting Command Frequency of the local oscillator/carrier signal f11 to f0
ページ15に含まれる内容の要旨
Si4421 Description of the Control Commands 1. Configuration Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h Bit el enables the internal data register. Bit ef enables the FIFO mode. If ef = 0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output. x3 x2 x1 x0 Crystal Load Capacitance [pF] 0 0 0 0 8.5 b1 b0 Frequency Band 0 0 0 1 9.0 0 0 Reserved 0 0 1 0 9.5 0 1 433 0 0 1 1 10.0 1 0 868 … 1 1 915 1
ページ16に含まれる内容の要旨
Si4421 Logic connections between power control bits: enable power amplifier enable et start TX power amplifier enable Edge RF front end detector clear TX latch enable enable es RF synthesizer RF synthesizer VCO and PLL start TX enable TX latch RF front end clear TX latch er enable baseband enable circuits crystal oscillator Crystal oscillator I/Q enable baseband demod circuits ebb Digital signal processing enable crystal oscillator ex clock and data out Note: If both et and e
ページ17に含まれる内容の要旨
Si4421 3. Frequency Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h The 12-bit parameter F (bits f11 to f0) should be in the range The constants C1 and C2 are determined by of 96 and 3903. When F value sent is out of range, the the selected band as: previous value is kept. The synthesizer center frequency f0 Band [MHz] C1 C2 can be calculated as: 433 1 43 f = 10 · C1 · (C2 + F/4000) [MHz] 0 868 2 43 915 3 30 Ban
ページ18に含まれる内容の要旨
Si4421 Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting: d1 d0 Response 0 0 Fast 0 1 Medium 1 0 Slow 1 1 Always on VDI Logic Diagram: MUX DQD d0 SEL0 CR_LOCK d1 SEL1 FAST IN0 DRSSI MEDIUM IN1 VDI Y SLOW DQD IN2 LOGIC HIGH IN3 CLR DRSSI DQD SET Q CR_LOCK er * R/S FF CLR Note: * For details see the Power Management Command Slow mode: The VDI signal will go high only if the DRSSI, DQD and the CR_LOCK (Clock Recovery Locked) signals present at the same time. It
ページ19に含まれる内容の要旨
Si4421 Bits 4-3 (g1 to g0): LNA gain select: g1 g0 Gain relative to maximum [dB] 0 0 0 0 1 -6 1 0 -14 1 1 -20 Bits 2-0 (r2 to r0): RSSI detector threshold: RSSI r2 r1 r0 setth 0 0 0 -103 0 0 1 -97 0 1 0 -91 0 1 1 -85 1 0 0 -79 1 0 1 -73 1 1 0 Reserved 1 1 1 Reserved The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSI =RSSI +G th setth LNA 6. Data Filter Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 0 0 1 0 al
ページ20に含まれる内容の要旨
Si4421 Bits 2-0 (f2 to f0): DQD threshold parameter. The Data Quality Detector is a digital processing part of the radio, connected to the demodulator - it is an indicator reporting the reception of an FSK modulated RF signal. It will work every time the receiver is on. Setting this parameter defines how clean incoming data stream would be stated as good data (valid FSK signal). If the internally calculated data quality value exceeds the DQD threshold parameter for five consecutive data bi
