ページ1に含まれる内容の要旨
H IGH B TFT AMLCD
®
T h e D e f i n i t i o n o f Q u a l i t y
OLOR 10.4" C RIGHTNESS
LC640.480.33-AC
Operations Manual
ページ2に含まれる内容の要旨
Copyright © 1999 by Planar Systems, Inc. Planar and The Definition of Quality are registered trademarks. is a trademark of Planar Systems, Inc. This document is subject to change without notice. Planar provides this information as reference only and does not imply any recommendation or endorsement of other vendor’s products. Date Description Document number OM600-01 May 1999 Revision Control ColorBrite
ページ3に含まれる内容の要旨
Contents ................................ ................................ ................................ .............. 3 Features and Benefits ................................ ................................ ................................ ................... 3 Installation and Handling ................................ ................................ ................................ ................. 4 Mounting the Display ................................ ................................
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Figure 1. Mounting Options. ................................ ................................ ................................ ........ 4 ................................ ................................ ................................ ....... 9 Figure 3. V ................................ ................................ ................................ .... 9 L ................................ ................................ ................................ ......... 10 .....................
ページ5に含まれる内容の要旨
The LC640.480.33-AC is a 1000 nit 10.4" diagonal VGA color AMLCD flat panel display module intended for commercial applications requiring outdoor viewability and long life. Special attention to the total backlight design gives the display a wide, “single- BEF” viewing angle while maintaining luminance efficiency greater than 45 nit/W. The display is convection cooled and does not require a fan, yet features a wide operating temperature range. It is lightweight, compact, and rugged, and includes
ページ6に含まれる内容の要旨
Installation and Handling Do not drop, bend, or flex the display. Do not allow objects to strike the surface of the display. using all four mounting hole locations. There are two recommended mounting configurations as shown in 1 using the hardware listed in Table 1 below. Appropriate changes to these mounting configurations may be needed to meet specific requirements or applications. Figure 1 . Mounting Options. Display Face Down Face Down Table 1 #6 SS, hex head or hex washer head
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Vent Clearance The LC640.480.33-AC display is a wide temperature display utilizing convection cooling. It is imperative to allow ambient air unrestricted access to the cooling vents in order to reliably operate the display at high temperatures The vents for the lamp cavity are along the top and bottom edges of the display with the openings facing the rear. The vents for the inverter cavity are along the top and bottom faces of the display: four along the top surface and four along the bottom sur
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Specifications Performance characteristics are guaranteed with the display at room temperature (25 °C) and with the operating voltage within specifications, unless otherwise specified. Optical performance is referenced to screen center at normal incidence and with the backlight at maximum luminance unless otherwise specified. Table 2 . Environmental Characteristics. Temperature Operating -10 to +70 °C -20 to +80 °C Storage -25 to +85 °C Operating 95% RH @ 40 ºC, Non-condensing, per IEC 68-2-3 O
ページ9に含まれる内容の要旨
Optical Characteristics Table 4 Luminance Typical 1000 NITs at screen center, initial 900 NITs at screen center, initial Contrast Ratio 150:1 typical 50:1 typical 3:1 typical Color Coordinates White field x = .339 typical y = .353 typical Luminance Control (typical) 50:1 initial, 100:1 stabilized (Lmax after > 15 minutes Ambient Light Sensor Visible light filtered ~420 to 675nm @ 50% pts. 0 to 3000 Lux typ.; assumes 18% scene reflectance Viewing Angle Horizontal ±70 degrees typ., White/black CR
ページ10に含まれる内容の要旨
Interfacing and Operation Power Requirements The LC640.480.33-AC display requires two power supplies: +5 Vdc for the LCD logic and +12 Vdc for the backlight. In Table 6 below, the backlight current and power are Table 6 . Input Power Min Max Units Backlight V +10.8 +12.0 +13.2 Vdc H V 0 – +16 Vdc Steady state current (V = +12 Vdc) I – 1.9 2.5 H H Peak start-up current (V = +12 Vdc) I – – 3.5 H Power (V = +12V) P – 23 30 W H H V 4.5 +5.0 +5.5 Vdc L V 0 – 6.0 Vdc V permissible ripple (V = +5V)
ページ11に含まれる内容の要旨
Figure 2 . Power Sequencing. Vcc 4.5V 4.5V where: t 10ms 1 ≤ 0< t 2 ≤ data 2.7V 0< t 3 ≤ t1 t2 t3 Applying video signals before V is applied may cause a latchup condition. Allowing V L L to remain “on” for a long period of time after video signals are removed—which stops the cell scanning—may produce a latent image. In addition, there is a restriction regarding dropouts on the V supply as illustrated in 3 (“Vcc”= V ). This is L L related to the reset circuit for the LCD’s internal logic. If a
ページ12に含まれる内容の要旨
Video Signal Characteristics Video signal inputs on J3 are digital inputs and are compatible with CMOS logic. Table 8 Description Minimum Maximum Units V -0.3 V + 0.3 Vdc I L V 0 0.3V Vdc L V 0.7V V Vdc L L 1 I – 1 I – 60 2 I – 1 IH1 I – 60 IH2 1. I applies to all signals except R/L and U/D. I applies to signals R/L and U/D. IL1 2. I applies to all signals except ENAB, U/D, and R/L. I applies to signals ENAB, U/D, IH1 IH2 and R/L. Video Modes recognition depends on the polarity of the sync sign
ページ13に含まれる内容の要旨
Signal Timing Video signal timing diagrams are shown in Figures 5, 6, and 7. The following table refers to these diagrams. Table . Video signal timing. Parameter Mode Min Max Units freq 1/Tc all – 25.18 28.33 MHz Tch all 5 – – Tcl all 10 – – Data Tds all 5 – – Tdh all 10 – – Horiz. TH all 30.0 31.78 – μ s all 750 800 900 clock PW THp all 2 96 200 clock Vertical TV 480 515 525 560 400 446 449 480 350 447 449 510 PW TVp all 1 – 34 THd all 640 640 640 clock Horiz. to clock THc all 10 – Tc-10 TVh al
ページ14に含まれる内容の要旨
Figure 5 . Timing Diagram, 480-line mode. c0.3Vc dVertical invalid data perio eNumber of V-data lin 0.3Vcc 0DH48 9DH47 TV TVd DH3 DH2 dHorizontal invalid data perio 0.3Vcc Number of H-data 0D64 DH1 Number of line D639 34 HT 0.3Vcc 0.7Vcc c0.3Vc Tcp dTH lTc hTd Tc D3 c0.7Vc Tch Tds D2 0.7Vcc Tcs TVs *C104 D1 c0.3Vc kNumber of cloc *C2 0.7Vcc TVp 2 c0.3Vc * Only when enable terminal is fixed "low" *C1 cTH 0.3Vcc 1 Vertical invalid data period c0.7Vc THc TVh 0.3Vcc 0.3Vcc THp 0.3Vcc dHorizontal inv
ページ15に含まれる内容の要旨
Figure 6 . Timing Diagram, 400-line mode. c0.7Vc dVertical invalid data perio eNumber of V-data lin 0.3Vcc 0DH40 9DH39 TV TVd DH3 Horizontal invalid data period DH2 0.3Vcc Number of H-data 0D64 DH1 eNumber of lin D639 34 HT 0.3Vcc 0.7Vcc 0.3Vcc Tcp THd Tcl hTd Tc D3 c0.3Vc Tch sTd D2 c0.7Vc Tcs TVs C104* D1 0.3Vcc Number of clock C2* c0.7Vc TVp 2 0.3Vcc * Only when enable terminal is fixed "low" *C1 THc 0.3Vcc 1 Vertical invalid data period 0.7Vcc THc TVh 0.3Vcc THp c0.3Vc Horizontal invalid dat
ページ16に含まれる内容の要旨
Figure 7 . Timing Diagram, 350-line mode. c0.3Vc dVertical invalid data perio eNumber of V-data lin 0.7Vcc 0DH35 9DH34 TV TVd DH3 dHorizontal invalid data perio DH2 0.3Vcc Number of H-data 0D64 DH1 Number of line D639 61 HT 0.3Vcc 0.7Vcc c0.3Vc Tcp dTH lTc hTd Tc D3 c0.7Vc Tch Tds D2 0.7Vcc Tcs TVs *C104 D1 c0.3Vc kNumber of cloc *C2 0.7Vcc TVp 2 c0.3Vc * Only when enable terminal is fixed "low" *C1 cTH 0.3Vcc 1 Vertical invalid data period c0.3Vc THc 0.3Vcc TVh 0.3Vcc THp 0.7Vcc dHorizontal inv
ページ17に含まれる内容の要旨
Video Characteristics Colors are developed in combination with 6-bit signals (64 steps in grayscale) of each primary red, green, and blue color. This process can result in up to 262,144 (64x64x64) colors. The mapping of the eighteen video data inputs is shown in Table 12 . Table Display colors R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Blue 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
ページ18に含まれる内容の要旨
Pixel Position The position of pixel data, relative to the color filter orientation and scan direction inputs is shown in 8 . Refer to the timing diagrams in Figures 5, 6, and 7 for horizontal pixel position (D1 through D640), and for vertical line position (DH1 Figure 8 . Pixel position of input data (480-line mode). D1,DH1 D2,DH1 D3,DH1 D640,DH1 D1,DH2 D2,DH2 D1,DH3 R G B D1,DH480 D640,DH480 The display image may be rotated 180 degrees using the R/L and U/D signals present on J3. Refer to Inve
ページ19に含まれる内容の要旨
Video Connector (J3) Video signals and LCD display power (V ) are applied via a polarized 34-pin dual-row 2 L mm pitch header with gold plated (30 μ ") contact surfaces and ejector/latching ears. The cable and connector options. Note that J3 is electrically and mechanically independent of Table . Video Connector (J3) Pinouts. Pin Signal Description Pin Signal Description 1 GND Ground 2 Dot Clock 3 4 5 GND Ground 6 R0 Red data (LSB) 7 R1 Red data 8 R2 Red data 9 R3 Red data 10 R4 Red data 11 R5 R
ページ20に含まれる内容の要旨
Dimming Connector (J2) inputs are applied via J2, which is a polarized 5-pin inline, 2.5 mm pitch header, tin plated with a friction lock. The connector is equivalent to the Molex 5268-NA ‘SPOX’ series housing, part number 50-37-5053 and Molex 5263 series crimp pin, part number 19 for more information. Table . Dimming Connector (J2) Pinouts. Pin Function 1 Pot high side voltage source output 2 3 GND 4 disable input 5 Backlight Power Connector (J1) Backlight power (V ) is applied via J1, which is
