Résumé du contenu de la page N° 1
CY7C64013C
CY7C64113C
Full-Speed USB (12-Mbps) Function
Full-Speed USB (12-Mbps) Function
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08001 Rev. *B Revised March 3, 2006
[+] Feedback
Résumé du contenu de la page N° 2
CY7C64013C CY7C64113C TABLE OF CONTENTS 1.0 FEATURES .......................................................................................................................................6 2.0 FUNCTIONAL OVERVIEW ..............................................................................................................7 3.0 PIN CONFIGURATIONS ..................................................................................................................9 4.0 PRODUCT SUMMARY TABLES .....
Résumé du contenu de la page N° 3
CY7C64013C CY7C64113C TABLE OF CONTENTS 16.6 DAC Interrupt ..........................................................................................................................31 16.7 GPIO/HAPI Interrupt ...............................................................................................................32 2 16.8 I C Interrupt .............................................................................................................................32 17.0 USB OVERVIEW .......
Résumé du contenu de la page N° 4
CY7C64013C CY7C64113C LIST OF FIGURES Figure 6-1. Clock Oscillator On-Chip Circuit ..........................................................................................17 Figure 7-1. Watchdog Reset (WDR) ......................................................................................................18 Figure 9-1. Block Diagram of a GPIO Pin ..............................................................................................19 Figure 9-2. Port 0 Data ......................
Résumé du contenu de la page N° 5
CY7C64013C CY7C64113C LIST OF TABLES Table 4-1. Pin Assignments ..................................................................................................................10 Table 4-2. I/O Register Summary .........................................................................................................10 Table 4-3. Instruction Set Summary ......................................................................................................12 Table 9-1. GPIO Port Output Control
Résumé du contenu de la page N° 6
CY7C64013C CY7C64113C 1.0 Features • Full-speed USB Microcontroller • 8-bit USB Optimized Microcontroller — Harvard architecture — 6-MHz external clock source — 12-MHz internal CPU clock — 48-MHz internal clock • Internal memory — 256 bytes of RAM — 8 KB of PROM (CY7C64013C, CY7C64113C) 2 • Integrated Master/Slave I C-compatible Controller (100 kHz) enabled through General-Purpose I/O (GPIO) pins • Hardware Assisted Parallel Interface (HAPI) for data transfer to external devices • I/O ports —
Résumé du contenu de la page N° 7
CY7C64013C CY7C64113C 2.0 Functional Overview The CY7C64013C and CY7C64113C are 8-bit One Time Programmable microcontrollers that are designed for full-speed USB applications. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. GPIO The CY7C64013C features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports (P0[7:0], P1[2:0], P2[6:2], P3[2:0])
Résumé du contenu de la page N° 8
CY7C64013C CY7C64113C Logic Block Diagram 6-MHz crystal PLL 48 MHz Clock 12-MHz Divider USB USB D+[0] Upstream 8-bit USB Port D–[0] SIE Transceiver CPU 12 MHz Interrupt PROM Controller 8 KB RAM GPIO P0[7:0] 256 byte PORT 0 P1[2:0] 6 MHz GPIO 12-bit PORT 1 P1[7:3] Timer CY7C64113C only P2[0,1,7] GPIO/ Watchdog HAPI P2[2]; Latch_Empty P2[3]; Data_Ready Timer PORT 2 P2[4]; STB P2[5]; OE P2[6]; CS Power-On Reset High Current P3[2:0] Outputs GPIO Additional PORT 3 P3[7:3] High Current Out
Résumé du contenu de la page N° 9
CY7C64013C CY7C64113C 3.0 Pin Configurations TOP VIEW CY7C64013C CY7C64013C CY7C64113C 28-pin SOIC 28-pin PDIP 48-pin SSOP XTALOUT 1 28 V 1 28 XTALOUT 1 48 V XTALOUT V CC CC CC 2 2 27 P1[1] 2 27 P1[0] 47 P1[1] XTALIN XTALIN XTALIN 3 26 P1[0] 3 26 P1[2] 3 46 P1[0] V V V REF REF REF 4 P1[2] 4 P1[2] GND 25 4 P3[0] P1[3] P1[1] 25 45 P3[0] P3[2] P1[4] P3[1] 5 24 GND 5 P1[5] 5 44 24 P3[2] P2[2] P1[6] D+[0] 6 23 P1[7] 6 43 P3[1] 6 23 GND P3[0] GND D–[0] 7 22 D+[0] 7 22 P3[1] 7 42 P2[2] P2[4] P3[2] P
Résumé du contenu de la page N° 10
CY7C64013C CY7C64113C 4.0 Product Summary Tables 4.1 Pin Assignments Table 4-1. Pin Assignments Name I/O 28-Pin SOIC 28-Pin PDIP 48-Pin SSOP Description D+[0], D–[0] I/O 6, 7 7, 8 7, 8 Upstream port, USB differential data. P0 I/O P0[7:0] P0[7:0] P0[7:0] GPIO Port 0 capable of sinking 7 mA (typical). 10, 14, 11, 15, 11, 15, 12, 16, 20, 26, 21, 27, 12, 16, 13, 17 13, 17, 14, 18 22, 28, 23, 29 P1 I/O P1[2:0] P1[2:0] P1[7:0] GPIO Port 1 capable of sinking 7 mA (typical). 25, 27, 26 26, 4, 27 6,
Résumé du contenu de la page N° 11
CY7C64013C CY7C64113C Table 4-2. I/O Register Summary (continued) Register Name I/O Address Read/Write Function Page GPIO Configuration 0x08 R/W GPIO Port Configurations 20 2 2 HAPI and I C Configuration 0x09 R/W HAPI Width and I C Position Configuration 24 USB Device Address A 0x10 R/W USB Device Address A 34 EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 35 EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 34 EP A1 Counter Register 0x13 R/W USB Addre
Résumé du contenu de la page N° 12
CY7C64013C CY7C64113C 4.3 Instruction Set Summary Refer to the CYASM Assembler User’s Guide for more details. Table 4-3. Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 00 7 NOP 20 4 ADD A,expr data 01 4 INC A acc 21 4 ADD A,[expr] direct 02 6 INC X x 22 4 ADD A,[X+expr] index 03 7 INC [expr] direct 23 7 ADC A,expr data 04 4 INC [X+expr] index 24 8 ADC A,[expr] direct 05 6 DEC A acc 25 4 ADC A,[X+expr] index 06 7 DEC X x 26 4 SUB A,expr data 07 4 DE
Résumé du contenu de la page N° 13
CY7C64013C CY7C64113C 5.0 Programming Model 5.1 14-Bit Program Counter (PC) The 14-bit program counter (PC) allows access to up to 8 KB of PROM available with the CY7C64x13C architecture. The top 32 bytes of the ROM in the 8 Kb part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes the application (see Interrupt V
Résumé du contenu de la page N° 14
CY7C64013C CY7C64113C 5.1.1 Program Memory Organization after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-µs timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x000A USB address A endpoint 1 interrupt vector 0x000C USB address A endpoint 2 interrupt vector 0x000E USB address A endpoint 3 interrupt vector 0x0010 USB address A endpoint 4 interrupt vector
Résumé du contenu de la page N° 15
CY7C64013C CY7C64113C 5.2 8-Bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-Bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section 5.6.3 for additional information. 5.4 8-Bit Program Stack Pointer (PSP) During a reset, the program stack pointer (PSP) is set to 0x00 and “grows” upward fr
Résumé du contenu de la page N° 16
CY7C64013C CY7C64113C 5.5 8-Bit Data Stack Pointer (DSP) The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP. During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data
Résumé du contenu de la page N° 17
CY7C64013C CY7C64113C 6.0 Clocking XTALOUT (pin 1) XTALIN To Internal PLL (pin 2) 30 pF 30 pF Figure 6-1. Clock Oscillator On-Chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide
Résumé du contenu de la page N° 18
CY7C64013C CY7C64113C 2 ms t WATCH Last write to No write to WDT Execution begins at Watchdog Timer register, so WDR Reset Vector 0x0000 Register goes HIGH Figure 7-1. Watchdog Reset (WDR) The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Register is cleared (see Section 18.1). Otherwise, the USB Controller would respond to all address 0 transactions. It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR e
Résumé du contenu de la page N° 19
CY7C64013C CY7C64113C 9.0 General-Purpose I/O (GPIO) Ports V CC GPIO mode CFG 2-bits OE Q1 Q2 Data Internal Out Data Bus Latch 14 kΩ GPIO Port Write PIN Q3* Data Port Read In Latch Reg_Bit STRB (Latch is Transparent except in HAPI mode) Data Interrupt Latch Interrupt Enable *Port 0,1,2: Low I sink Interrupt Port 3: High I sink Controller Figure 9-1. Block Diagram of a GPIO Pin There are up to 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and P3[7:0]) for the hardware interface. The number of GPI
Résumé du contenu de la page N° 20
CY7C64013C CY7C64113C Port 3 Data ADDRESS 0x03 Bit # 7 6543 210 Bit Name P3.7 P3.6 P3.5 P3.4 P3.3 P32 P3.1 P3.0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1111 111 Figure 9-5. Port 3 Data Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is left floating, the leakage current caused
