Résumé du contenu de la page N° 1
APPLICATION NOTE
SH7263/SH7203 Group
Data Transfer to On-chip Peripheral Modules with DMAC
Introduction
This application note provides an example of transferring data to on-chip peripheral modules with the direct memory
access controller (DMAC) of the SH7263/SH7203.
Target Device
SH7263/SH7203
Contents
1. Introduction ....................................................................................................................................... 2
2. Description of Sample Applic
Résumé du contenu de la page N° 2
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 1. Introduction 1.1 Specification • DMAC channel 1 is used to transfer data from external memory to the transmit FIFO data register (SCFTDR) in the serial communication interface with FIFO (SCIF channel 0) in order to transmit character string data. • SCIF transmit FIFO data empty transfer requests (on-chip peripheral module request) are used to request DMA transfer. 1.2 Modules Used • Direct memory access con
Résumé du contenu de la page N° 3
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 2. Description of Sample Application In this sample application, the DMAC and on-chip peripheral module requests are used to transfer data from external memory to the SCIF. 2.1 Operational Overview of Modules Used When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of channels, and continues the transfer operation until the transfer end condition is met. Tran
Résumé du contenu de la page N° 4
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC DMAC module RDMATCR_n On-chip Iteration memory DMATCR_n control On-chip RSAR_n peripheral Register module control SAR_n RDAR_n Start-up control DAR_n DMA transfer request signal CHCR_n DMA transfer acknowledge signal Request HEIn priority DMAOR Interrupt controller control DEIn DMARS0 to DMARS3 External ROM Bus interface External RAM External device (memory mapped) Bus state External device controller (with
Résumé du contenu de la page N° 5
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 2.2 Procedure for Setting Used Modules This section describes the procedure for making initial settings when the DMAC is to be used to transfer data from memory to on-chip peripheral modules. On-chip peripheral module requests are used for transfer requests. A flowchart of DMAC initialization is shown in figure 2. For details on registers, refer to the SH7263/SH7203 Group Hardware Manual. [1] Enabling clock supply
Résumé du contenu de la page N° 6
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 2.3 Operation of Sample Program In this sample program, SCIF transmit FIFO data empty transfer requests are made to activate DMAC channel 1, and to transfer data from external memory to the transmit FIFO data register (SCFTDR) on SCIF channel 0. The data written to SCFTDR on SCIF channel 0 are transmitted in UART mode. An operation timing of the sample program is shown in figure 3. DMA transfer using SCIF transmit F
Résumé du contenu de la page N° 7
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 2.4 Processing Procedure of Sample Program In this sample program, character string data stored in external memory are transferred by DMA to the transmit FIFO data register (SCFTDR) on SCIF channel 0, and then are transmitted in UART mode. The register settings for the sample program are listed in table 2. The macro definitions used in this sample program are also listed in table 3. A flowchart of the sample program
Résumé du contenu de la page N° 8
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC Table 3 Macro Definitions Used in Sample Program Macro Definition Setting Value Description DMA_SIZE_BYTE H'0000 Byte transfer DMA_SIZE_WORD H'0001 Word transfer DMA_SIZE_LONG H'0002 Longword transfer DMA_SIZE_LONGx4 H'0003 16-byte transfer DMA_INT_DISABLE H'0000 DMA transfer end interrupt disabled DMA_INT_ENABLE H'0010 DMA transfer end interrupt enabled START Initialize DMAC/enable transfer io_init_dma1() I
Résumé du contenu de la page N° 9
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 3. Sample Program 1. Sample Program Listing "main.c" (1) 1 /*""FILE COMMENT""************************************************************** 2 * 3 * System Name : SH7203 Sample Program 4 * File Name : main.c 5 * Contents : Data transfer to on-chip peripheral modules with DMAC 6 * Version : 1.00.00 7 * Model : M3A-HS30 8 * CPU : SH7203 9 * Compiler : SHC9.1.1.0 10 * note : Sample program for transfe
Résumé du contenu de la page N° 10
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 2. Sample Program Listing "main.c" (2) 54 /* ---- Values for baud rate specification ---- */ 55 enum{ 56 CBR_1200, 57 CBR_2400, 58 CBR_4800, 59 CBR_9600, 60 CBR_19200, 61 CBR_31250, 62 CBR_38400, 63 CBR_57600, 64 CBR_115200 65 }; 66 67 /* ==== Table of register setting values ==== */ 68 static SH7203_BAUD_SET scif_baud[] = { 69 {214, 1}, /* 1200bps (-0.07%) */ 70
Résumé du contenu de la page N° 11
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 3. Sample Program Listing "main.c" (3) 107 /* ==== Enabling SCIF0 initialization/transfer ==== */ 108 io_init_scif0(CBR_115200); 109 /* Communication mode :UART mode */ 110 /* Bit rate :115.2Kbps */ 111 /* TXI interrupt is generated when data in transmit FIFO is one byte */ 112 /* ==== Disabling DMA transfer ==== */ 113 io_dma1_stop(); 114 while(1){ 115 /* Program end */
Résumé du contenu de la page N° 12
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 4. Sample Program Listing "main.c" (4) 161 /* ----Setting DMA source address register---- */ 162 DMAC.SAR1.LONG = (unsigned long)src; 163 164 /* ----Setting DMA reload source address register---- */ 165 DMAC.RSAR1.LONG = (unsigned long)src; 166 167 /* ----Setting DMA destination address register---- */ 168 DMAC.DAR1.LONG = (unsigned long)dst; 169 170 /* ----Setting DMA reload destination address register
Résumé du contenu de la page N° 13
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 5. Sample Program Listing "main.c" (5) 217 bit6 : DS : DREQ select :0 Low level Unused 218 bit5 : TB : cycle :0--------------- Cycle-stealing mode 219 bit4-3 : TS : transfer size:B'00--- Byte transfer 220 bit2 : IE : interrupt enable:0--- Disable interrupt 221 bit1 : TE : transfer end---------- 222 bit0 : DE : DMA enable bit:0----- DMA 223 */ 224 225 /* ----Setting DMA extension r
Résumé du contenu de la page N° 14
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 6. Sample Program Listing "main.c" (7) 272 * Function : Initializes SCIF0 273 * : Asynchronous (UART)/ 8 bits/ No parity/ 1 stop bit/ RTS/CTS disabled 274 * : Baud rate is specified by argument bps 275 * : 276 *----------------------------------------------------------------------- 277 * Argument : int bps : Value for baud rate specification 278 *--------------------------------------------------
Résumé du contenu de la page N° 15
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC 4. Documents for Reference • Software Manual SH-2A, SH2A-FPU Software Manual The most up-to-date version of this document is available on the Renesas Technology Website. • Hardware Manual SH7203 Group Hardware Manual SH7263 Group Hardware Manual The most up-to-date version of this document is available on the Renesas Technology Website. REJ06B0734-0100/Rev.1.00 April 2008 Page 15 of 17
Résumé du contenu de la page N° 16
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com Revision Record Description Rev. Date Page Summary 1.00 Apr.17.08 — First edition issued All trademarks and registered trademarks are the property of their respective owners. REJ06B0734-0100/Rev.1.00 Apr
Résumé du contenu de la page N° 17
SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third
