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User’s Manual
µPD789489 Subseries
8-Bit Single-Chip Microcontrollers
µPD789488
µPD789489
µPD78F9488
µPD78F9489
Document No. U15331EJ4V1UD00 (4th edition)
Date Published July 2005 NS CP(K)
©
Printed in Japan
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[MEMO] 2 User’s Manual U15331EJ4V1UD
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HAND
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EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. These commodities, technology o
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• The information in this document is current as of July, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifica
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Major Revisions in This Edition Page Description Throughout Change of descriptions of µPD789489, 78F9489 • Change of status from under development to development completed • Change of the subseries name to “µPD789489 subseries” pp.31 to 33 Update of 1.5 78K/0S Series Lineup to latest version p.123 Modification of Figure 7-2 Block Diagram of Timer 50 p.124 Modification of Figure 7-3 Block Diagram of Timer 60 p.126 Modification of Figure 7-5 Block Diagram of Output control circuit (Time
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INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the µPD789489 Subseries and design and develop application systems and programs for these devices. Target products: • µPD789489 Subseries: µPD789488, 789489, 78F9488, 78F9489 Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization Two manuals are available for the µPD789489 Subseries: This manual a
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Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary ve
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Documents Related to Flash Memory Writing Document Name Document No. PG-FP3 Flash Memory Programmer User’s Manual U13502E PG-FP4 Flash Memory Programmer User’s Manual U15260E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semicondu
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CONTENTS CHAPTER 1 GENERAL ..........................................................................................................................26 1.1 Features ......................................................................................................................................26 1.2 Applications ...............................................................................................................................26 1.3 Ordering Information............
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3.1.4 Data memory addressing ..............................................................................................................54 3.2 Processor Registers ..................................................................................................................58 3.2.1 Control registers............................................................................................................................58 3.2.2 General-purpose registers.........................
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5.4.5 When subsystem clock is not used ............................................................................................. 104 5.4.6 Subsystem clock ×4 multiplication circuit .................................................................................... 104 5.5 Clock Generator Operation.....................................................................................................105 5.6 Changing Setting of System Clock and CPU Clock ............................
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9.4.1 Operation as watchdog timer ......................................................................................................171 9.4.2 Operation as interval timer ..........................................................................................................172 CHAPTER 10 10-BIT A/D CONVERTER ............................................................................................173 10.1 10-Bit A/D Converter Functions.......................................
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14.1 Multiplier Function...................................................................................................................267 14.2 Multiplier Configuration ..........................................................................................................267 14.3 Multiplier Control Register......................................................................................................269 14.4 Multiplier Operation.........................................
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CHAPTER 20 MASK OPTIONS ...........................................................................................................331 CHAPTER 21 INSTRUCTION SET ......................................................................................................332 21.1 Operation ..................................................................................................................................332 21.1.1 Operand identifiers and description methods .................
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LIST OF FIGURES (1/6) Figure No. Title Page 2-1 I/O Circuit Types ..........................................................................................................................................46 3-1 Memory Map (µPD789488)..........................................................................................................................48 3-2 Memory Map (µPD78F9488)...........................................................................................................
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LIST OF FIGURES (2/6) Figure No. Title Page 5-5 Format of Subclock Control Register............................................................................................................99 5-6 Subclock Selection Register Format ..........................................................................................................100 5-7 External Circuit of Main System Clock Oscillator........................................................................................101 5-
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LIST OF FIGURES (3/6) Figure No. Title Page 7-21 Timing of Square-Wave Output with 16-Bit Resolution ..............................................................................149 7-22 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N))........................................151 7-23 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N))........................................152 7-24 Timing of Carrier Generator Operation (When CR60 = CRH60 = N
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LIST OF FIGURES (4/6) Figure No. Title Page 11-4 Format of Asynchronous Serial Interface Mode Register 20 ......................................................................191 11-5 Format of Asynchronous Serial Interface Status Register 20.....................................................................193 11-6 Format of Baud Rate Generator Control Register 20 .................................................................................194 11-7 Format of Asynchronous Ser
