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CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces
PRELIMINARY
MAY 2004
CP3BT26 Reprogrammable Connectivity Processor with
®
Bluetooth , USB, and CAN Interfaces
1.0 General Description
The CP3BT26 connectivity processor combines high perfor-
advanced power-saving modes achieve new design points
mance with the massive integration needed for embedded in the trade-off between battery size and operating time for
Bluetooth applications. A powerful RISC core with on-chip handheld a
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Table of Contents 16.3 ADC Operation in Power-Saving Modes . . . . . . . . . . . . . . . . . . . 83 1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16.4 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.0 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 16.5 ADC Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.0 Device Overview . . . .
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CP3BT26 Power-down modes 2.0 Features Flexible I/O CPU Features Up to 54 general-purpose I/O pins (shared with on-chip Fully static RISC processor core, capable of operating peripheral I/O) from 0 to 24 MHz with zero wait/hold states Programmable I/O pin characteristics: TRI-STATE out- Minimum 41.7 ns instruction cycle time with a 24-MHz in- put, push-pull output, weak pull-up input, high-imped- ternal clock frequency, based on a 12-MHz external input ance input 47 independently vectored p
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3.0 Device Overview The CP3BT26 connectivity processor is a complete micro- 3.3 INPUT/OUTPUT PORTS computer with all system timing, interrupt logic, program The device has up to 54 software-configurable I/O pins, or- memory, data memory, and I/O ports included on-chip, mak- ganized into seven ports called Port B, Port C, Port E, Port ing it well-suited to a wide range of embedded applications. G, Port H, Port I, and Port J. Each pin can be configured to The block diagram on page 1 shows the majo
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CP3BT26 3.7 BLUETOOTH LLC 3.11 ADVANCED AUDIO INTERFACE The integrated hardware Bluetooth Lower Link Controller The audio interface provides a serial synchronous, full-du- (LLC) complies to the Bluetooth Specification Version 1.1 plex interface to CODECs and similar serial devices. Trans- and integrates the following functions: mit and receive paths operate asynchronously with respect to each other. Each path uses three signals for communica- 4.5K-byte dedicated Bluetooth Data RAM tion: shift c
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3.14 RANDOM NUMBER GENERATOR 3.18 TIMING AND WATCHDOG MODULE RNG peripheral for use in Trusted Computer Peripheral Ap- The Timing and Watchdog Module (TWM) contains a Real- plications (TCPA) to improve the authenticity, integrity, and Time timer and a Watchdog unit. The Real-Time Clock Tim- privacy of Internet-based communication and commerce. ing function can be used to generate periodic real-time based system interrupts. The timer output is one of 16 in- 3.15 MICROWIRE/SPI puts to the Multi-In
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CP3BT26 In the normal mode of operation, the interface only transfers 3.21 POWER MANAGEMENT one word at a periodic rate. In the network mode, the inter- The Power Management Module (PMM) improves the effi- face transfers multiple words at a periodic rate. The periodic ciency of the device by changing the operating mode and rate is also called a data frame and each word within one power consumption to match the required level of activity. frame is called a slot. The beginning of each new data fra
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4.0 Signal Descriptions 12 MHz Crystal X1CKI/BBCLK X1CKI/BBCLK PB[7:0] PB[7:0] 12 MHz Crystal 8 8 GPIO or Ext. Clock or Ext. Clock X1CKO X1CKO PC[7:0] PC[7:0] 8 8 A[22:0] X2CKI 32.768 kHz 32.768 kHz X2CKI 23 SEL0 Crystal Crystal X2CKO X2CKO External SEL1 Bus AVCC AVCC SEL2 1 1 Interface AGND AGND SELIO 1 1 ADVCC ADVCC 1 WR0 1 Power ADGND ADGND Power CP3BT26 1 CP3BT26 WR1 1 Supply Supply VCC VCC 6 RD 6 (LQFP-144) (LQFP-128) GND GND 6 6 RFDATA RFDATA IOVCC IOVCC 15 10 PGO/RFSYNC PGO/RFSYNC IOGND I
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CP3BT26 Table 2 CP3BT26 LQFP-128 Signal Descriptions Alternate Name Pins I/O Primary Function Alternate Function Name X1CKI 1 Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None Output 32 kHz Oscillator Output None None X2CKO 1 Input Chip general reset None None RESET 1 Special mode select input with ENV0 1 I/O PLLCLK PLL Clock Output internal pull-up during reset Special mo
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Alternate Name Pins I/O Primary Function Alternate Function Name ADC3 1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact ADC4 1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0 ADC5 1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1 ADC6 1 Input ADC Input Channel 6 None None ADC7 1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode) VREFP 1 Input ADC Positive Voltage Reference None None PB[7:0] 8 I/O Generic I/O None None PC[7:0] 8 I/O Generic I/O None None PE0 1 I/
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CP3BT26 Alternate Name Pins I/O Primary Function Alternate Function Name PG4 1 I/O Generic I/O SDAT BT Serial I/F Data PG5 1 I/O Generic I/O SLE BT Serial I/F Load Enable Output WUI10 Multi-Input Wake-Up Channel 10 PG6 1 I/O Generic I/O BTSEQ2 Bluetooth Sequencer Status TA Multi Function Timer Port A 1 I/O Generic I/O PG7 BTSEQ3 Bluetooth Sequencer Status RXD1 UART Channel 1 Receive Data Input 1 I/O Generic I/O PH0 WUI11 Multi-Input Wake-Up Channel 11 TXD1 UART Channel 1 Transmit Data Output PH
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Table 3 CP3BT26 LQFP-144 Signal Descriptions Alternate Name Pins I/O Primary Function Alternate Function Name X1CKI 1 Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None Output 32 kHz Oscillator Output None None X2CKO 1 Input Chip general reset None None RESET 1 Special mode select input with ENV0 1 I/O PLLCLK PLL Clock Output internal pull-up during reset Special mode selec
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CP3BT26 Alternate Name Pins I/O Primary Function Alternate Function Name ADC3 1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact ADC4 1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0 ADC5 1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1 ADC6 1 Input ADC Input Channel 6 None None ADC7 1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode) VREFP 1 Input ADC Positive Voltage Reference None None PB[7:0] 8 I/O Generic I/O D[7:0] External Data Bus Bits 0 to 7 PC[7:0] 8
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Alternate Name Pins I/O Primary Function Alternate Function Name STD AAI Transmit Data Output PF6 1 I/O Generic I/O TIO7 Versatile Timer Channel 7 SRD AAI Receive Data Input PF7 1 I/O Generic I/O TIO8 Versatile Timer Channel 8 PG0 1 I/O Generic I/O RFSYNC BT AC Correlation/TX Enable Output PG1 1 I/O Generic I/O RFCE BT RF Chip Enable Output BTSEQ1 Bluetooth Sequencer Status 1 I/O Generic I/O PG2 SRCLK AAI Receive Clock 1 I/O Generic I/O SCLK BT Serial I/F Shift Clock Output PG3 1 I/O Generic I/
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CP3BT26 5.0 CPU Architecture The CP3BT26 uses the CR16C third-generation 16-bit When the CFG.SR bit is clear, register pairs are grouped CompactRISC processor core. The CPU implements a Re- in the manner used by native CR16C software: (R1,R0), duced Instruction Set Computer (RISC) architecture that al- (R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP. lows an effective execution rate of up to one instruction per R12, R13, RA, and SP are 32-bit registers for holding ad- clock cycle. For a d
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5.2.4 Interrupt Base Register (INTBASE) N The Negative bit indicates the result of the last comparison operation, with the operands in- The INTBASE register holds the address of the dispatch ta- terpreted as signed integers. ble for exceptions. The dispatch table can be located any- – Second operand greater than or equal to 0 where in the CPU address space. When loading the first operand. INTBASE register, bits 31 to 24 and bit 0 must written with 0. 1 – Second operand less than first operand.
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CP3BT26 5.4 CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various oper- ating modes and to control optional on-chip caches. Be- cause the CP3BT26 does not have cache memory, the cache control bits in the CFG register are reserved. All CFG bits are cleared on reset. 15 10 9 8 7 6 5 2 1 0 Reserved SR ED 0 0 Reserved 0 0 ED The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch ta- ble (IDT) is 16 or 32 bits. Each entry holds the addres
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5.5 ADDRESSING MODES In another example, the operand resides in memory. Its address is obtained by The CR16C CPU core implements a load/store architec- adding a displacement encoded in the in- ture, in which arithmetic and logical instructions operate on struction to the contents of register r5. register operands. Memory operands are made accessible The address calculation does not modify in registers using load and store instructions. For efficient the contents of register r5. implementation of
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CP3BT26 5.6 STACKS 5.7 INSTRUCTION SET A stack is a last-in, first-out data structure for dynamic stor- Table 4 lists the operand specifiers for the instruction set, age of data and addresses. A stack consists of a block of and Table 5 is a summary of all instructions. For each in- memory used to hold the data and a pointer to the top of the struction, the table shows the mnemonic and a brief de- stack. As more data is pushed onto a stack, the stack grows scription of the operation performed. d
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Table 5 Instruction Set Summary Mnemonic Operands Description MOVi Rsrc/imm, Rdest Move MOVXB Rsrc, Rdest Move with sign extension MOVZB Rsrc, Rdest Move with zero extension MOVXW Rsrc, RPdest Move with sign extension MOVZW Rsrc, RPdest Move with zero extension MOVD imm, RPdest Move immediate to register-pair RPsrc, RPdest Move between register-pairs ADD[U]i Rsrc/imm, Rdest Add ADDCi Rsrc/imm, Rdest Add with carry ADDD RPsrc/imm, RPdest Add with RP or immediate. MACQWa Rsrc1, Rsrc2, RPdest Multi
