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MPC8260UM/D
4/1999
Rev. 0
ª
MPC8260 PowerQUICC II
UserÕs Manual
ª
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PowerQUICC II, Mfax, and DigitalDNA are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, PowerPC 604e, and RS/6000 are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. 2 I C is a registered trademark of Philips Semiconductors Information in this document is provided solely to enable system and software implemen
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Overview 1 PowerPC Processor Core 2 Memory Map 3 System Interface Unit (SIU) 4 Reset 5 External Signals 6 60x Signals 7 The 60x Bus 8 Clocks and Power Control 9 Memory Controller 10 Secondary (L2) Cache Support 11 IEEE 1149.1 Test Access Port 12 Communications Processor Module Overview 13 Serial Interface with Time-Slot Assigner 14 CPM Multiplexing 15 Baud-Rate Generators (BRGs) 16 Timers 17 SDMA Channels and IDMA Emulation 18 Serial Communications Controllers (SCCs) 19 SCC UART Mode 20 SCC
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1 Overview PowerPC Processor Core 2 Memory Map 3 System Interface Unit (SIU) 4 Reset 5 External Signals 6 60x Signals 7 The 60x Bus 8 Clocks and Power Control 9 Memory Controller 10 Secondary (L2) Cache Support 11 IEEE 1149.1 Test Access Port 12 Communications Processor Module Overview 13 14 Serial Interface with Time-Slot Assigner CPM Multiplexing 15 Baud-Rate Generators (BRGs) 16 Timers 17 SDMA Channels and IDMA Emulation 18 Serial Communications Controllers (SCCs) 19 SCC UART Mode 20 SCC
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CONTENTS Paragraph Page Title Number Number About This Book Before Using this ManualÑImportant Note.......................................................... lv Audience ................................................................................................................ lv Organization.......................................................................................................... lvi Suggested Reading...............................................................
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CONTENTS Paragraph Page Title Number Number 1.7.2 Bus Configurations.........................................................................................1-15 1.7.2.1 Basic System ..............................................................................................1-15 1.7.2.2 High-Performance Communication ...........................................................1-16 1.7.2.3 High-Performance System Microprocessor ...............................................1-17 Chapte
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CONTENTS Paragraph Page Title Number Number 2.5.1 PowerPC Exception Model............................................................................2-22 2.5.2 MPC8260 Implementation-Specific Exception Model..................................2-23 2.5.3 Exception Priorities........................................................................................2-26 2.6 Memory Management ........................................................................................2-26 2.6.1 Po
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CONTENTS Paragraph Page Title Number Number 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR) ...............................4-28 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) .............4-28 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)............................4-29 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)...4-30 4.3.2.6 SIU Module Configuration Register (SIUMCR) .......................................4-31 4.
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CONTENTS Paragraph Page Title Number Number External Signals 6.1 Functional Pinout .................................................................................................6-1 6.2 Signal Descriptions ..............................................................................................6-2 Chapter 7 60x Signals 7.1 Signal Configuration ............................................................................................7-2 7.2 Signal Descriptions ............
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CONTENTS Paragraph Page Title Number Number 7.2.5.2 Address Retry (ARTRY)............................................................................7-11 7.2.5.2.1 Address Retry (ARTRY)ÑOutput.........................................................7-11 7.2.5.2.2 Address Retry (ARTRY)ÑInput ...........................................................7-11 7.2.6 Data Bus Arbitration Signals..........................................................................7-12 7.2.6.1 Data Bus Gran
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CONTENTS Paragraph Page Title Number Number 8.4.3.1 Transfer Type Signal (TT[0Ð4]) Encoding ................................................8-10 8.4.3.2 Transfer Code Signals TC[0Ð2] .................................................................8-13 8.4.3.3 TBST and TSIZ[0Ð3] Signals and Size of Transfer...................................8-13 8.4.3.4 Burst Ordering During Data Transfers.......................................................8-14 8.4.3.5 Effect of Alignment on Data Tr
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CONTENTS Paragraph Page Title Number Number 9.8 System Clock Control Register (SCCR) ..............................................................9-8 9.9 System Clock Mode Register (SCMR) ................................................................9-9 9.10 Basic Power Structure ........................................................................................9-10 Chapter 10 Memory Controller 10.1 Features.................................................................
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CONTENTS Paragraph Page Title Number Number 10.4.5 Bank Interleaving ........................................................................................10-36 10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA) .............................10-37 10.4.6 SDRAM Device-Specific Parameters ..........................................................10-38 10.4.6.1 Precharge-to-Activate Interval.................................................................10-38 10.4.6.2 Activate to Read/Wri
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CONTENTS Paragraph Page Title Number Number 10.6.4.1.4 Loop Control ........................................................................................10-76 10.6.4.1.5 Repeat Execution of Current RAM Word (REDO) ............................10-76 10.6.4.2 Address Multiplexing ...............................................................................10-77 10.6.4.3 Data Valid and Data Sample Control .......................................................10-77 10.6.4.4 Signals
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CONTENTS Paragraph Page Title Number Number 12.5 MPC8260 Restrictions .....................................................................................12-30 12.6 Nonscan Chain Operation ................................................................................12-30 Chapter 13 Communications Processor Module Overview 13.1 Features ..............................................................................................................13-1 13.2 MPC8260 Serial Configu
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CONTENTS Paragraph Page Title Number Number Chapter 14 Serial Interface with Time-Slot Assigner 14.1 Features...............................................................................................................14-3 14.2 Overview ............................................................................................................14-4 14.3 Enabling Connections to TSA ............................................................................14-7 14.4 Serial Interfa
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CONTENTS Paragraph Page Title Number Number Chapter 16 Baud-Rate Generators (BRGs) 16.1 BRG Configuration Registers 1Ð8 (BRGCx).....................................................16-2 16.2 Autobaud Operation on a UART .......................................................................16-4 16.3 UART Baud Rate Examples ..............................................................................16-5 Chapter 17 Timers 17.1 Features .......................................
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CONTENTS Paragraph Page Title Number Number 18.5.3 Controlling 60x Bus Bandwidth...................................................................18-12 18.6 IDMA Priorities................................................................................................18-12 18.7 IDMA Interface Signals....................................................................................18-12 18.7.1 DREQx and DACKx ...........................................................................
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CONTENTS Paragraph Page Title Number Number 19.3.5.2 Asynchronous Protocols ..........................................................................19-21 19.3.6 Digital Phase-Locked Loop (DPLL) Operation...........................................19-22 19.3.6.1 Encoding Data with a DPLL....................................................................19-24 19.3.7 Clock Glitch Detection.................................................................................19-26 19.3.8 Recon
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CONTENTS Paragraph Page Title Number Number Chapter 21 SCC HDLC Mode 21.1 SCC HDLC Features ..........................................................................................21-2 21.2 SCC HDLC Channel Frame Transmission.........................................................21-2 21.3 SCC HDLC Channel Frame Reception..............................................................21-3 21.4 SCC HDLC Parameter RAM ................................................................
