Résumé du contenu de la page N° 1
Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G. Fettweis chair
Digital Signal Transmission Lab
SS 08
Oliver Arnold
Steffen Kunze
Résumé du contenu de la page N° 2
Introduction chair Hardware Why to use digital signal processing? General introduction to DSPs The TMS320C6711 DSP Architecture Overview Peripherals DSK6711 evaluation board - Software Code Composer Studio DSP/BIOS Multi-channel Buffered Serial Port (McBSP) TU Dresden, 4/29/2008 Slide 2
Résumé du contenu de la page N° 3
chair Hardware TU Dresden, 4/29/2008 Slide 3
Résumé du contenu de la page N° 4
Digital Signal Processing (DSP) chair Wireless / Cellular HDD Voice-band audio PRML read channel RF codecs MR pre-amp Voltage regulation Servo control SCSI tranceivers Consumer Audio DSP: Automotive Stereo A/D, D/A PLL Digital radio A/D/A Technology Mixers Active suspension Enabler Voltage regulation Multimedia Stereo audio DTAD Imaging Speech synthesizer Graphics palette Mixed-signal Voltage regulation processor TU Dresden, 4/29/2008 Slide 4
Résumé du contenu de la page N° 5
System Considerations chair Performance Performance Interfacing Interfacing Power Power Size Size Ease-of Use Integration Ease-of Use Integration Cost Cost • Programming • Memory • Programming • Memory • Device cost • Device cost • • Interfacing Interfacing • • Peripherals Peripherals • System cost • System cost • Debugging • Debugging • Development cost • Development cost • Time to market • Time to market TU Dresden, 4/29/2008 Slide 5
Résumé du contenu de la page N° 6
Why Go Digital? chair Digital signal processing techniques are now so powerful that sometimes it is extremely difficult, if not impossible, for analogue signal processing to achieve similar performance. Examples: FIR filter with linear phase Adaptive filters TU Dresden, 4/29/2008 Slide 6
Résumé du contenu de la page N° 7
Why Go Digital? chair Analogue signal processing is achieved by using analogue components such as: Resistors Capacitors Inductors The inherent tolerances associated with these components, temperature, voltage changes and mechanical vibrations can dramatically affect the effectiveness of the analogue circuitry TU Dresden, 4/29/2008 Slide 7
Résumé du contenu de la page N° 8
Why Go Digital? chair With DSP? - It is easy to: Change applications Correct applications Update applications Additionally DSPs reduce: Noise susceptibility Chip count Development time Cost Power consumption TU Dresden, 4/29/2008 Slide 8
Résumé du contenu de la page N° 9
chair General Introduction to DSPs TU Dresden, 4/29/2008 Slide 9
Résumé du contenu de la page N° 10
What Problem Are We Trying To Solve? chair xY ADC DAC DSP Digital sampling of Most DSP algorithms can be an analog signal: expressed as: count A Y = Σ a * x i i i = 1 for (i = 1; i < count; i++){ t sum += m[i] * n[i]; } TU Dresden, 4/29/2008 Slide 10
Résumé du contenu de la page N° 11
What are the typical DSP algorithms? chair The Sum of Products (SOP) is the key element in most DSP algorithms: Algorithm Equation M yn () = a x(n −k) ∑ k Finite Impulse Response Filter k =0 M N y(n) = a x(n −k) + b y(n −k) k k ∑ ∑ Infinite Impulse Response Filter k =0 k =1 N y(n) = x(k)h(n −k) ∑ Convolution k =0 N −1 X (k) = x(n) exp[ −j(2 π / N)nk] ∑ Discrete Fourier Transform n =0 N −1 π ⎡ ⎤ F() u = c(u).f (x).cos u() 2x +1 ∑ ⎢ ⎥ Discrete Cosine Transform 2N ⎣ ⎦ x =0 TU Dresden, 4/29/2008 S
Résumé du contenu de la page N° 12
Why do we need DSP processors? chair Use a DSP processor when the following are required: Cost saving Smaller size Low power consumption Processing of many “high” frequency signals in real-time Use a GPP processor when the following are required: Large memory Advanced operating systems TU Dresden, 4/29/2008 Slide 12
Résumé du contenu de la page N° 13
Hardware vs. Microcode multiplication chair DSP processors are optimized to perform multiplication and addition operations. Multiplication and addition are done in hardware and in one cycle. Example: 4-bit multiply (unsigned). Hardware Microcode Hardware Microcode 1011 1011 1011 1011 x 1110 x 1110 x 1110 x 1110 10011010 10011010 0000 Cycle 1 0000 Cycle 1 1011. Cycle 2 1011. Cycle 2 1011.. Cycle 3 1011.. Cycle 3 1011... Cycle 4 1011... Cycle 4 10011010 Cycle 5 10011010 Cycle 5 TU Dresden, 4/
Résumé du contenu de la page N° 14
General Purpose DSP vs. DSP in ASIC chair Application Specific Integrated Circuits (ASICs) are semiconductors designed for dedicated functions. The advantages and disadvantages of using ASICs are listed below: Advantages Disadvantages Advantages Disadvantages • High throughput • High investment cost • High throughput • High investment cost • Lower silicon area • Less flexibility • Lower silicon area • Less flexibility • Lower power consumption • Long time from design to • Lower power consu
Résumé du contenu de la page N° 15
Floating vs. Fixed point processors chair Applications which require: High precision Wide dynamic range High signal-to-noise ratio Ease of use Need a floating point processor Drawback of floating point processors: Higher power consumption Usually higher cost Usually slower than fixed-point counterparts and larger in size TU Dresden, 4/29/2008 Slide 15
Résumé du contenu de la page N° 16
chair TMS320C6711 Architectural Overview TU Dresden, 4/29/2008 Slide 16
Résumé du contenu de la page N° 17
General DSP System Block Diagram chair Internal Memory Internal Buses P E External R I Memory P Central H E Processing R A Unit L S TU Dresden, 4/29/2008 Slide 17
Résumé du contenu de la page N° 18
‘6711 CPU Overview chair Specification Clock Rate: 100/150 MHz 600/900 MFLOPS 0.18- μm/5-Level Metal Process – CMOS Technology CPU has got two Datapaths, altogether: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture 2*16 32-Bit General-Purpose Registers TU Dresden, 4/29/2008 Slide 18
Résumé du contenu de la page N° 19
‘6711 CPU Overview chair VelociTI advanced very-long instruction words (VLIW) Program Memory Width is 256 Bit Up to 8 32-Bit instructions can be executed in parallel/Cycle 16, 32 and 40 bit fixed point operands 32 and 64 bit floating point operands Instruction parallelism is detected at compile-time no data dependency checking is done in Hardware. Instruction Packing Reduces Code Size All operations work on registers Memory Architecture 4K-Byte L1P Program Cache (Direct Mapped) 4K-
Résumé du contenu de la page N° 20
Functional Block and CPU Diagram chair TU Dresden, 4/29/2008 Slide 20
