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Intel® Xeon® Processor E5-1600
v2/E5-2600 v2 Product Families
Datasheet - Volume One of Two
September 2013
Reference Number: 329187-001
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IN U SA NFORMA L LE E S AND/ S O TT ION O HERW R U IN S T E IS O H E IS FA I G D NREED O TE CU L P MEN IN RO D W TU IS RC IT T PROV IN S IG N C B ID L YU IN ED DIT IN N EG L L CON , T IH ABI E IN NE LCT IT TY E ION LO PROD R W WIA TR U HR C Inte AN TS TA l® IR ES E N PROD RE OL TA D U TC IENG T SS I. G T N N O O ED F LI IT N C N O EE R N S S IN S E, F T Ex O ER Np A D rED eP sA s FOR * R O TIC R A U IMPL N LAR Y A P IED PPL UR ,ICA B PO YS E TE IO S , M T N O IN E PPEL RC W H OR H AICH T NT O AB
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Table of Contents 1Overview................................................................................................................. 11 1.1 Introduction ..................................................................................................... 11 1.1.1 Processor Feature Details ........................................................................ 14 1.1.2 Supported Technologies .......................................................................... 14 1.2 Interfaces ....
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3.2.3 AES Instructions.....................................................................................80 3.2.4 Execute Disable Bit .................................................................................81 3.3 Intel® Secure Key .............................................................................................81 3.4 Intel® OS Guard ...............................................................................................81 3.5 Intel® Hyper-Threading Technology.......
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6.9 Processor Asynchronous Sideband and Miscellaneous Signals ................................ 122 6.10 Processor Power and Ground Supplies................................................................ 125 7 Electrical Specifications......................................................................................... 127 7.1 Processor Signaling ......................................................................................... 127 7.1.1 System Memory Interface Signal Groups .........
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10.3 Fan Power Supply [STS200C]............................................................................228 10.3.1 Boxed Processor Cooling Requirements....................................................229 10.4 Boxed Processor Contents.................................................................................232 Figures 1-1 Intel® Xeon® Processor E5-1600 v2 Product Family on the 1 Socket Platform ........................................................................................
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2-42 Processor ID Construction Example...................................................................... 60 2-43 RdIAMSR() ....................................................................................................... 61 2-44 PCI Configuration Address .................................................................................. 63 2-45 RdPCIConfig()................................................................................................... 64 2-46 PCI Configuration Addre
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1-3 Referenced Documents.......................................................................................22 2-1 Summary of Processor-specific PECI Commands ....................................................30 2-2 Minor Revision Number Meaning ..........................................................................33 2-3 GetTemp() Response Definition ...........................................................................34 2-4 RdPkgConfig() Response Definition.......................
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6-11 System Reference Clock (BCLK{0/1}) Signals ..................................................... 121 6-12 JTAG and TAP Signals ...................................................................................... 121 6-13 SVID Signals .................................................................................................. 122 6-14 Processor Asynchronous Sideband Signals .......................................................... 122 6-15 Miscellaneous Signals .....................
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Revision History Revision Description Revision Date Number 001 • Initial Release September 2013 § 10 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families Datasheet Volume One of Two
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Overview 1 Overview 1.1 Introduction The Intel® Xeon® processor E5-1600 v2/E5-2600 v2 product families datasheet- Volume One provides DC electrical specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. This document is intended to be distributed as a part of the complete document which consists of two volumes. The structure and scope of the two volumes are provided in Table 1-2. The
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Overview Table 1-1. HCC, MCC, and LCC SKU Table Summary Die Size TDP (W) Model Number Core Count Low-Core Count 130W 2U E5-2637 v2 4 130W 1S E5-1660 v2 6 E5-1650 v2 130W 1S E5-1620 v2 4 95W 1U E5-2630 v2 6 80W 1U E5-2630 v2 6 E5-2620 v2 80W 1U E5-2609 v2 4 E5-2603 v2 60W 1U E5-2630L v2 6 Some processor features are not available on all platforms. Refer to the Intel® Xeon® Processor E5 v2 Product Family Specification Update for details of each processor SKU. The Intel® Xeon® processor E5-160
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. . . x1 x4 . . . x1 x4 Overview Table 1-2. Volume Structure and Scope (Sheet 2 of 2) • Configuration Process and Registers • Processor Integrated I/O (IIO) Configuration Registers • Processor Uncore Configuration Registers Figure 1-1. Intel® Xeon® Processor E5-1600 v2 Product Family on the 1 Socket Platform ethernet Processor SATA “Legacy” PCIe DMI2 PCH PCIe B I O S x16 x16 x8 Figure 1-2. Intel® Xeon® Processor E5-2600 v2 Product Family on the 2 Socket Platform ethernet QPI Processor Pro
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Overview 1.1.1 Processor Feature Details • Up to 12 execution cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 24 threads per socket • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core •Up to 30 MB last level cache (LLC): up to 2.5 MB per core instruction/data la
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Overview • Independent channel mode or lockstep mode • Data burst length of eight cycles for all memory organization modes • Memory DDR3 data transfer rates of 800, 1066, 1333, 1600, and 1866 MT/s • 64-bit wide channels plus 8-bits of ECC support for each channel • DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V • 1-GB, 2-GB, and 4-GB DDR3 DRAM technologies supported for these devices: — UDIMMs x8, x16 — RDIMMs x4, x8 — LRDIMM x4, x8 (2-Gb and 4-Gb only) LR-DIMMs are supporte
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Overview • Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{01/23}_N 1.2.2 PCI Express* • The PCI Express* port(s) are fully-compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports • 4 lanes of PCI E
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Overview • Power Management Event (PME) functions. • Message Signaled Interrupt (MSI and MSI-X) messages • Degraded Mode support and Lane Reversal support • Static lane numbering reversal and polarity inversion support • Support for PCIe* 3.0 atomic operation, PCIe 3.0 optional extension on atomic read-modify-write mechanism • Additional read buffers for point-point transfers. This increases the number of outstanding transactions in point-point transfers across same processor sockets, from
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Overview • Static lane numbering reversal support • Supports DMI2 virtual channels VC0, VC1, VCm, and VCp 1.2.4 Intel® QuickPath Interconnect (Intel® QPI) • Compliant with Intel QuickPath Interconnect v1.1 standard packet formats • Implements two full width Intel QPI ports • Full width port includes 20 data lanes and 1 clock lane • 64 byte cache-lines • Isochronous access support is not available on any CPU model containing two home agents. Note: RAS support depends on processor SKU. For exa
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Overview 1.3 Power Management Support 1.3.1 Processor Package and Core States • ACPI C-states as implemented by the following processor C-states: — Package: PC0, PC1/PC1e, PC2, PC3, PC6 (Package C7 is not supported) — Core: CC0, CC1, CC1E, CC3, CC6 (Processor Core C7 is not supported) • Enhanced Intel SpeedStep® Technology 1.3.2 System States Support • S0, S1, S3, S4, S5 1.3.3 Memory Controller • Multiple CKE power down modes • Multiple self-refresh modes • Memory thermal monitoring via MEM_H
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Overview 1.6 Terminology Term Description ASPM Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core. DDR3 Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM DMA Direct Memory Access DMI Direct Media Interface DMI2 Direct Media Interface Gen 2 DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel Allows the operating system
