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®
Intel 80200 Processor based on
® ™
Intel XScale Microarchitecture
Developer’s Manual
March, 2003
Order Number: 273411-003
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including lia
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Contents 1 Introduction .............................................................................................. 1 ® ® ™ 1.1 Intel 80200 Processor based on Intel XScale Microarchitecture High-Level Overview.........1 1.1.1 ARM* Architecture Compliance ...................................................................................1 1.1.2 Features...........................................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 3.2.2.1 Page (P) Attribute Bit................................................................................2 3.2.2.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits ............................2 3.2.2.3 Instruction Cache......................................................................................2 3.2.2.4 Data Cache and Write Buffer....................................................................3 3.2.2.5 De
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 6.2.3.3 Write Miss Policy ......................................................................................7 6.2.3.4 Write-Back Versus Write-Through ............................................................7 6.2.4 Round-Robin Replacement Algorithm .........................................................................8 6.2.5 Parity Protection .............................................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 9.3 Programmer Model.......................................................................................................................2 9.3.1 INTCTL ........................................................................................................................3 9.3.2 INTSRC .......................................................................................................................4 9.3.3 INTSTR..........
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 12.5.3 Instruction Fetch Latency Mode...................................................................................8 12.5.4 Data/Bus Request Buffer Full Mode ............................................................................9 12.5.5 Stall/Writeback Statistics .............................................................................................9 12.5.6 Instruction TLB Efficiency Mode .......................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 13.11.6.4 DBG.V ....................................................................................................25 13.11.6.5 DBG.RX..................................................................................................25 13.11.6.6 DBG.D ....................................................................................................25 13.11.6.7 DBG.FLUSH .........................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 14.4.10 Miscellaneous Instruction Timing.................................................................................9 14.4.11 Thumb* Instructions.....................................................................................................9 ® A Compatibility: Intel 80200 Processor vs. SA-110................................ 1 A.1 Introduction.............................................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture B.4.1 Instruction Cache...........................................................................................................17 B.4.1.1. Cache Miss Cost...............................................................................................17 B.4.1.2. Round Robin Replacement Cache Policy.........................................................17 B.4.1.3. Code Placement to Reduce Cache Misses .........................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture C.2.2 TAP Pins..........................................................................................................................3 C.2.3 Instruction Register (IR)...................................................................................................4 C.2.3.1.Boundary-Scan Instruction Set ...........................................................................4 C.2.4 TAP Test Data Registers .................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Figures ® ® ™ 1-1 Intel 80200 Processor based on Intel XScale Microarchitecture Features ........................................... 2 3-1 Example of Locked Entries in TLB.............................................................................................................. 9 4-1 Instruction Cache Organization .................................................................................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Tables 2-1 Multiply with Internal Accumulate Format...................................................................................................4 2-2 MIA{} acc0, Rm, Rs.........................................................................................................................4 2-3 MIAPH{} acc0, Rm, Rs...................................................................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 9-1 Interrupt Control Register (CP13 register 0) ................................................................................................ 3 9-2 Interrupt Source Register (CP13, register 4) ................................................................................................ 4 9-3 Interrupt Steer Register (CP13, register 8) ........................................................................................
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture 14-14 Semaphore Instruction Timings ....................................................................................................................9 14-15 CP15 Register Access Instruction Timings...................................................................................................9 14-16 CP14 Register Access Instruction Timings.....................................................................................
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Introduction 1 ® ® ™ 1.1 Intel 80200 Processor based on Intel XScale Microarchitecture High-Level Overview ® ® ™ The Intel 80200 processor based on Intel XScale microarchitecture, is the next generation in ® the Intel StrongARM* processor family (compliant with ARM* Architecture V5TE). It is ® designed for high performance and low-power; leading the industry in mW/MIPs. The Intel 80200 processor integrates a bus controller and an interrupt controller around a core processor, with intended e
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Introduction 1.1.2 Features ® Figure 1-1 shows the major functional blocks of the Intel 80200 processor. The following sections give a brief, high-level overview of these blocks. ® ® ™ Figure 1-1. Intel 80200 Processor based on Intel XScale Microarchitecture Features Data Cache Mini-Data Instruction Max 32 Kbytes Cache Cache 32 ways wr-back or 2 Kbytes 32 Kbytes wr-through 2 ways 32 ways Hit under Data RAM Lockable by line miss
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Introduction 1.1.2.2 Memory Management ® The Intel 80200 processor implements the Memory Management Unit (MMU) Architecture specified in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to physical address translation. The MMU Architecture also specifies the caching policies for the instruction cache and data memory. These policies are specified as page attributes and include: identifyi
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® ® ™ Intel 80200 Processor based on Intel XScale Microarchitecture Introduction 1.1.2.6 Power Management ® The Intel 80200 processor supports two low power modes: idle and sleep. These modes are discussed in Section 8.3, “Power Management” on page 8-5. 1.1.2.7 Interrupt Controller ® An interrupt controller is implemented on the Intel 80200 processor that provides masking of interrupts and the ability to steer interrupts to FIQ or IRQ. It is accessed through Coprocessor 13 registers. See Chap
