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8XC196L x Supplement to
8XC196K x, 8XC196J x,
87C196CA User’s Manual
August 2004
Order Number: 272973-003
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, mer
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 RELATED DOCUMENTS .............................................................................................. 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 MICROCONTROLLER FEATURES .............................................................................. 2-1 2.2 BLOCK DIAGRAM.....................................................
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8XC196LX SUPPLEMENT CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT 6.1 SSIO 0 CLOCK REGISTER........................................................................................... 6-1 6.2 SSIO 1 CLOCK REGISTER........................................................................................... 6-2 CHAPTER 7 EVENT PROCESSOR ARRAY 7.1 EPA FUNCTIONAL OVERVIEW ................................................................................... 7-1 7.1.1 EPA Mask Registers ..........................
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CONTENTS 8.6 PROGRAMMING THE J1850 CONTROLLER ............................................................ 8-16 8.6.1 Programming the J1850 Command (J_CMD) Register ..........................................8-16 8.6.2 Programming the J1850 Configuration (J_CFG) Register ......................................8-18 8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register ...........................8-19 8.6.4 Programming the J1850 Status (J_STAT) Register .....................................
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8XC196LX SUPPLEMENT FIGURES Figure Page 2-1 8XC196Lx Block Diagram ............................................................................................2-2 2-2 Clock Circuitry (87C196LA, LB Only) ...........................................................................2-3 2-3 Internal Clock Phases (Assumes PLL is Bypassed).....................................................2-4 2-4 Effect of Clock Mode on Internal CLKOUT Frequency.................................................2-5 2-5
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CONTENTS FIGURES Figure Page 11-1 Slave Programming Circuit.........................................................................................11-3 11-2 Serial Port Programming Circuit.................................................................................11-4 A-1 87C196LA 52-pin PLCC Package............................................................................... A-3 A-2 87C196LB 52-pin PLCC Package.............................................................................
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8XC196LX SUPPLEMENT TABLES Table Page 1-1 Related Documents......................................................................................................1-2 2-1 Features of the 8XC196Lx and 8XC196Kx Product Famiies .......................................2-1 2-2 State Times at Various Frequencies ............................................................................2-4 2-3 Relationships Between Input Frequency, Clock Multiplier, and State Times ...............2-5 2-4 UPROM Programmi
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1 Guide to This Manual
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CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual. It describes the differences between the 8XC196Lx and the 8XC196Kx family of microcontrollers. For information not found in this supplement, please consult the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual (order number 272258) or the 8XC196Lx datasheets listed in the “Related Documents” section of this chapter. 1.1 MANUAL CONTENTS This supple
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8XC196LX SUPPLEMENT Appendix A — Signal Descriptions — provides reference information for the 8XC196Lx de- vice pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments. Glossary — defines terms with special meaning used throughout this supplement. Index — lists key topics with page number references. 1.2 RELATED DOCUMENTS Table 1-1 lists additional documents that you may find useful in designing systems incorporating the 8XC196Lx m
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2 Architectural Overview
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CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB, and 83C196LD) and the 8XC196Kx (8XC196Kx, 8XC196Jx, and 87C196CA) microcontroller families. Both the 8XC196Lx and the 8XC196Kx are designed for high-speed calculations and fast I/O, and share a common architecture and instruction set with few deviations. This chapter provides a high-level overview of the deviations between the two families. NOTE ® This supplement describes
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8XC196LX SUPPLEMENT 2.2 BLOCK DIAGRAM Figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller. Observe that the slave port peripheral does not exist on the 8XC196Lx. Optional Core Interrupt (CPU, Memory ROM/ Controller Controller) OTPROM Optional Peripheral Clock and Code/Data Transaction Power Mgmt. RAM Server I/O SIO SSIO EPA A/D WDT J1850 Note: The J1850 peripheral is unique to the 87C196LB device. The A/D peripheral is unique to the 87C196LA, LB device
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ARCHITECTURAL OVERVIEW Disable Phase Filter PLL Comparator (Powerdown) F XTAL1 XTAL1 Phase-locked Oscillator Phase-locked Loop PLLEN Clock Multiplier XTAL2 1 Disable Oscillator (Powerdown) 0 f Disable Clock Input (Powerdown) Divide by two Circuit To reset logic f/2 Disable Clocks (Idle, Powerdown) Clock CPU Clocks (PH1, PH2) Clock Failure Generators Detection Peripheral Clocks (PH1, PH2) f/2 Programmable OSC Divider (CLK1:0) 0 CLKOUT 1 Disable Clocks (Powerdown) A5290-01 Figure 2-2. Clock Circui
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8XC196LX SUPPLEMENT XTAL1 tt 1 State Time 1 State Time PH1 PH2 CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0805-01 Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed) The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2. State Times at Various Frequencies f (Frequency Input to the State Time Divide-by-two Circuit) 8 MHz 250 ns 12 MHz 167 ns
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ARCHITECTURAL OVERVIEW T XHCH XTAL1 (16 MHz) f PLLEN = 0 t = 62.5ns Internal CLKOUT f PLLEN = 1 t = 31.25ns Internal CLKOUT A3376-01 Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times F f t XTAL1 (Frequency PLLEN Multiplier (Input Frequency to (Clock State Time on XTAL1) the Divide-by-two Circuit) Period) 4 MHz 0 1 4 MHz 250 ns 500 ns 8 MHz 0 1 8 MHz 125 ns 250 ns 12 MHz 0 1 12 MHz 83.5 ns 167 ns 16
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8XC196LX SUPPLEMENT Address: 1FF2H USFR1 (read only) Reset State: XXH The UPROM special-function register 1 (USFR1) reflects the status of unerasable, programmable read-only memory (UPROM) locations. This read-only register reflects the status of two bits that control the output frequency on CLKOUT. 7 0 — — — — — — CLK1 CLK0 Bit Bit Function Number Mnemonic 7:2 — Reserved. 1:0 CLK1:0 CLKOUT Control These bits reflect the programmed frequency of the CLKOUT signal: CLK1 CLK0 0 0 divide by 1 (CL
