Résumé du contenu de la page N° 1
™
Intel386 EX
Embedded Microprocessor
User’s Manual
™
Intel386 EXTB
Embedded
Microprocessor
™
Intel386 EXTC
Embedded
Microprocessor
Résumé du contenu de la page N° 2
™ Intel386 EX Embedded Microprocessor User’s Manual 1996
Résumé du contenu de la page N° 3
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in- fringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor variations to this specification known as errata. *Other brands and names are the pro
Résumé du contenu de la page N° 4
CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-3 1.3 SPECIAL TERMINOLOGY ............................................................................................ 1-4 1.4 RELATED DOCUMENTS .............................................................................
Résumé du contenu de la page N° 5
Intel386™ EX MICROPROCESSOR USER’S MANUAL 4.5.2 Enabling and Disabling the Expanded I/O Space .....................................................4-8 4.5.2.1 Programming REMAPCFG Example ...................................................................4-8 4.6 ADDRESSING MODES................................................................................................. 4-9 4.6.1 DOS-compatible Mode .............................................................................................
Résumé du contenu de la page N° 6
CONTENTS 6.3.4 Interrupt Acknowledge Cycle ..................................................................................6-23 6.3.5 Halt/Shutdown Cycle ...............................................................................................6-26 6.3.6 Refresh Cycle .........................................................................................................6-28 6.3.7 BS8 Cycle ..................................................................................................
Résumé du contenu de la page N° 7
Intel386™ EX MICROPROCESSOR USER’S MANUAL 7.3.4.2 SMRAM State Dump Area .................................................................................7-14 7.3.5 Resume Instruction (RSM) ......................................................................................7-15 7.4 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS ....................................... 7-15 7.5 PROGRAMMING CONSIDERATIONS........................................................................ 7-16 7.5.1 System Man
Résumé du contenu de la page N° 8
CONTENTS 9.3.3 Initialization Command Word 1 (ICW1) ...................................................................9-20 9.3.4 Initialization Command Word 2 (ICW2) ...................................................................9-21 9.3.5 Initialization Command Word 3 (ICW3) ...................................................................9-22 9.3.6 Initialization Command Word 4 (ICW4) ...................................................................9-24 9.3.7 Operation Command Word 1
Résumé du contenu de la page N° 9
Intel386™ EX MICROPROCESSOR USER’S MANUAL CHAPTER 11 ASYNCHRONOUS SERIAL I/O UNIT 11.1 OVERVIEW ................................................................................................................. 11-1 11.1.1 SIO Signals .............................................................................................................11-3 11.2 SIO OPERATION ........................................................................................................ 11-4 11.2.1 Baud-rate Genera
Résumé du contenu de la page N° 10
CONTENTS 12.2.4 Bus Control Arbitration ............................................................................................12-9 12.2.5 Ending DMA Transfers ..........................................................................................12-10 12.2.6 Buffer-transfer Modes ...........................................................................................12-12 12.2.6.1 Single Buffer-Transfer Mode ............................................................................
Résumé du contenu de la page N° 11
Intel386™ EX MICROPROCESSOR USER’S MANUAL 13.2.3 Receiver ................................................................................................................13-12 13.3 REGISTER DEFINITIONS......................................................................................... 13-16 13.3.1 Pin Configuration Register (PINCFG) ...................................................................13-17 13.3.2 SIO and SSIO Configuration Register (SIOCFG) ...................................
Résumé du contenu de la page N° 12
CONTENTS 15.2.3 Refresh Addresses .................................................................................................15-4 15.2.4 Bus Arbitration ........................................................................................................15-5 15.3 RCU OPERATION....................................................................................................... 15-5 15.4 REGISTER DEFINITIONS................................................................................
Résumé du contenu de la page N° 13
Intel386™ EX MICROPROCESSOR USER’S MANUAL CHAPTER 18 JTAG TEST-LOGIC UNIT 18.1 OVERVIEW ................................................................................................................. 18-1 18.2 TEST-LOGIC UNIT OPERATION................................................................................ 18-3 18.2.1 Test Access Port (TAP) ..........................................................................................18-3 18.2.2 Test Access Port (TAP) Controller ...........
Résumé du contenu de la page N° 14
CONTENTS APPENDIX D SYSTEM REGISTER QUICK REFERENCE D.1 PERIPHERAL REGISTER ADDRESSES..................................................................... D-1 D.2 CLKPRS ....................................................................................................................... D-7 D.3 CSnADH (UCSADH)..................................................................................................... D-8 D.4 CSnADL (UCSADL)..............................................................
Résumé du contenu de la page N° 15
Intel386™ EX MICROPROCESSOR USER’S MANUAL D.37 OCW1 (MASTER AND SLAVE).................................................................................. D-40 D.38 OCW2 (MASTER AND SLAVE).................................................................................. D-41 D.39 OCW3 (MASTER AND SLAVE).................................................................................. D-42 D.40 P1CFG....................................................................................................
Résumé du contenu de la page N° 16
CONTENTS APPENDIX E INSTRUCTION SET SUMMARY E.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY.................................. E-1 E.2 INSTRUCTION ENCODING....................................................................................... E-22 E.2.1 32-bit Extensions of the Instruction Set ................................................................ E-23 E.2.2 Encoding of Instruction Fields ............................................................................... E-24 E.2.2.1 Encod
Résumé du contenu de la page N° 17
Intel386™ EX MICROPROCESSOR USER’S MANUAL FIGURES Figure Page 2-1 Intel386™ EX Embedded Processor Block Diagram ...................................................2-2 3-1 Instruction Pipelining ....................................................................................................3-2 3-2 The Intel386™ CX Processor Internal Block Diagram .................................................3-3 4-1 PC/AT I/O Address Space (10-bit Decode)....................................................
Résumé du contenu de la page N° 18
CONTENTS FIGURES Figure Page 6-16 Intel386 EX Processor to SRAM/FLASH Interface.....................................................6-41 6-17 Intel386 EX Processor to PSRAM Interface...............................................................6-42 6-18 Intel386 EX Processor to Paged DRAM Interface......................................................6-43 6-19 Intel386 EX Processor and Non-Paged DRAM Interface...........................................6-44 7-1 Standard SMI# ....................
Résumé du contenu de la page N° 19
Intel386™ EX MICROPROCESSOR USER’S MANUAL FIGURES Figure Page 10-7 Mode 1 – Writing a New Count.................................................................................10-10 10-8 Mode 2 – Basic Operation........................................................................................10-11 10-9 Mode 2 – Disabling the Count ..................................................................................10-11 10-10 Mode 2 – Writing a New Count.......................................
Résumé du contenu de la page N° 20
CONTENTS FIGURES Figure Page 11-21 Modem Control Register (MCRn).............................................................................11-30 11-22 Modem Status Register (MSRn)...............................................................................11-31 11-23 Scratch Pad Register (SCRn)...................................................................................11-32 12-1 DMA Unit Block Diagram.....................................................................................
