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STK14C88-5
256 Kbit (32K x 8) AutoStore nvSRAM
Features Functional Description
■ 35 ns and 45 ns access times The Cypress STK14C88-5 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
■ Hands off automatic STORE on power down with external 68
elements incorporate QuantumTrap technology producing the
µF capacitor
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
■ STORE to Quantum
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STK14C88-5 Pin Configurations Figure 2. Pin Diagram: 32-Pin LCC Figure 1. Pin Diagram: 32-Pin DIP Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. 0 14 DQ -DQ Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. 0 7 Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO WE W pins is written to the specific address location. Input
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STK14C88-5 having a capacitor of between 68uF and 220uF (+ 20%) rated at Device Operation 6V should be provided. The voltage on the V pin is driven to CAP 5V by a charge pump internal to the chip. A pull up is placed on The STK14C88-5 nvSRAM is made up of two functional compo- WE to hold it inactive during power up. nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM Figure 3. AutoStore Mode memory cell operates as a standard fast
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STK14C88-5 Figure 4. AutoStore Inhibit Mode If the STK14C88-5 is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system V or between CE and system V . CC CC Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14C88-5 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific addre
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STK14C88-5 Figure 5. Current Versus Cycle Time (READ) Data Protection The STK14C88-5 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when V is less than V . If the STK14C88-5 is in a CC SWITCH WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadverten
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STK14C88-5 manufacturing test to ensure these system routines work Best Practices consistently. nvSRAM products have been used effectively for over 15 years. ■ Power up boot firmware routines should rewrite the nvSRAM While ease of use is one of the product’s main system values, into the desired state. While the nvSRAM is shipped in a preset experience gained working with hundreds of applications has state, best practice is to again rewrite the nvSRAM into the resulted in the following sugg
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STK14C88-5 Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V Maximum Ratings 0-7 Power Dissipation.......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the DC output Current (1 output at a time, 1s duration) .... 15 mA device. These user guidelines are not tested. Storage Temperature ................................. –65 °C to +150 °C Operating Range Temperature under Bias ............................. –55 °C to +12
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STK14C88-5 Capacitance [8] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 5pF IN A V = 0 to 3.0V CC C Output Capacitance 7pF OUT Thermal Resistance [8] In the following table, the thermal resistance parameters are listed. Parameter Description Test Conditions 32-CDIP 32-LCC Unit Θ Thermal Resistance Test conditions follow standard test methods TBD TBD °C/W JA (Junction to Ambient) and proced
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STK14C88-5 AC Switching Characteristics SRAM Read Cycle Parameter 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Chip Enable Access Time 35 45 ns ACE ELQV [9] t t Read Cycle Time 35 45 ns t AVAV, ELEH RC [10] t Address Access Time 35 45 ns t AVQV AA t t Output Enable to Data Valid 15 20 ns DOE GLQV [10] t Output Hold After Address Change 5 5 ns t AXQX OHA [11] t Chip Enable to Output Active 5 5 ns t ELQX LZCE [11] t Chip Disable to Output Inactive 13 15 ns t EHQZ HZ
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STK14C88-5 SRAM Write Cycle Parameter 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Write Cycle Time 35 45 ns WC AVAV t t t Write Pulse Width 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 25 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 ns SA AVWL, AVEL t t t Address Hold A
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STK14C88-5 AutoStore or Power Up RECALL STK14C88-5 Parameter Alt Description Unit Min Max [15] t Power up RECALL Duration 550 μs t RESTORE HRECALL [16] t STORE Cycle Duration 10 ms t HLHZ STORE [16] t t Time Allowed to Complete SRAM Cycle 1 μs t HLQZ , BLQZ DELAY V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.6 V RESET t V Rise Time 150 μs VCCRISE CC [13] Low Voltage Trigger (V ) to HSB low 300 ns t SWITCH VSBL Switching Waveforms Figure 12. AutoStore/Power Up REC
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STK14C88-5 Software Controlled STORE/RECALL Cycle [19] The software controlled STORE/RECALL cycle follows. 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max [16] t STORE/RECALL Initiation Cycle Time 35 45 ns t AVAV RC [18, 19] t Address Setup Time 0 0 ns t AVEL SA [18, 19] t Clock Pulse Width 25 30 ns t ELEH CW [18, 19] t Address Hold Time 20 20 ns t ELAX HACE t RECALL Duration 20 20 μs RECALL Switching Waveforms [19] Figure 13. CE Controlled Software STORE/RECALL Cycle t t RC RC AD
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STK14C88-5 Hardware STORE Cycle STK14C88-5 Parameter Alt Description Unit Min Max [16, 20] t t Hardware STORE High to Inhibit Off 700 ns t RECOVER, HHQX DHSB t t Hardware STORE Pulse Width 15 ns PHSB HLHX t Hardware STORE Low to STORE Busy 300 ns HLBL Switching Waveforms Figure 14. Hardware STORE Cycle Note 20. t is only applicable after t is complete. DHSB STORE Document Number: 001-51038 Rev. ** Page 13 of 17 [+] Feedback
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STK14C88-5 Part Numbering Nomenclature STK14C88 - 5 C 35 M Temperature Range: M - Military (-55 to 125°C) Speed: 35 - 35 ns 45 - 45 ns Package: C = Ceramic 32-pin 300 mil DIP K = Ceramic 32-pin 300 mil DIP (Solder dip finish) L = Ceramic 32-pin LLC Retention / Endurance 5 5 = Military (10 years or 10 cycles) Ordering Information Speed Operating Ordering Code Package Diagram Package Type (ns) Range 35 STK14C88-5C35M 001-51694 32-pin CDIP (300 mil) Military STK14C88-5K35M 001-51694 32-pin CDIP
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STK14C88-5 Package Diagram Figure 15. 32-Pin (300-Mil) Side Braze DIL (001-51694) 001-51694 ** Document Number: 001-51038 Rev. ** Page 15 of 17 [+] Feedback
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STK14C88-5 Package Diagram (continued) Figure 16. 32-Pad (450-Mil) LCC (51-80068) 51-80068-** Document Number: 001-51038 Rev. ** Page 16 of 17 [+] Feedback
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STK14C88-5 Document History Page Document Title: STK14C88-5 256 Kbit (32K x 8) AutoStore nvSRAM Document Number: 001-51038 Orig. of Submission Rev ECN No. Description of Change Change Date ** 2666844 GVCH/PYRS 03/02/09 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Produc
