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SL811HS
SL811HS Embedded USB Host/Slave Controller
Features Introduction
• First USB Host/Slave controller for embedded systems in The SL811HS is an Embedded USB Host/Slave Controller
the market with a standard microprocessor bus interface capable of communicating in either full speed or low speed.
The SL811HS interfaces to devices such as microprocessors,
• Supports both full speed (12 Mbps) and low speed (1.5
microcontrollers, DSPs, or directly to a variety of buses such
Mbps) USB transfer
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SL811HS Data Port, Microprocessor Interface mode described in Auto Address Increment Mode, where direct addressing is used to READ/WRITE to an individual The SL811HS microprocessor interface provides an 8-bit address. bidirectional data path along with appropriate control lines to interface to external processors or controllers. Programmed USB transactions are automatically routed to the memory I/O or memory mapped I/O designs are supported through the buffer that is configured for that tran
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SL811HS PLL Clock Generator Typical Crystal Requirements Either a 12 MHz or a 48 MHz external crystal is used with the The following are examples of ‘typical requirements.’ Note that [1] SL811HS . Two pins, X1 and X2, are provided to connect a these specifications are generally found as standard crystal low cost crystal circuit to the device as shown in Figure 2 and values and are less expensive than custom values. If crystals Figure 3. Use an external clock source if available in the appli- a
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SL811HS “SL811HS Slave Mode Registers” on page 12 describes Slave All other register’s power up and reset in an unknown state and register definitions). Access to the registers are through the firmware for initialization. microprocessor interface similar to normal RAM accesses USB Control Registers (see “Bus Interface Timing Requirements” on page 26) and provide control and status information for USB transactions. Communication and data flow on the USB bus uses the SL811HS’ USB A-B Control re
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SL811HS USB-A/USB-B Host Control Registers [Address = 00h, 08h] . Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Preamble Data Toggle Bit SyncSOF ISO Reserved Direction Enable Arm Bit Position Bit Name Function 7 Preamble If bit = ’1’ a preamble token is transmitted before transfer of low speed packet. If bit = ’0’, preamble generation is disabled. • The SL811HS automatically generates preamble packets when bit 7 is se
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SL811HS USB-A/USB-B Host Base Length [Address = 02h, 0Ah]. Table 5. USB-A / USB-B Host Base Length Definition [Address 02h, 0Ah] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HBL7 HBL6 HBL5 HBL4 HBL3 HBL2 HBL1 HBL0 The USB A/B Host Base Length register contains the maximum packet size transferred between the SL811HS and a slave USB peripheral. Essentially, this designates the largest packet size that is transferred by the SL811HS. Base Length designates the size of data packet sent or recei
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SL811HS USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining (from Host Base Length value) after a packet is transferred. For example, if the Base Length register is set to 0x040 and an IN Token was sent to the peripheral device. If, after the transfer is complete, the value of the Host Transfer Count is 0x10
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SL811HS Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as follows. Table 11. Control Register 1 [Address 05h] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Suspend USB Speed J-K state force USB Engine Reserved Reserved SOF ena/dis Reset Bit Position Bit Name Function 7 Reserved ‘0’ 6 Suspend ’1’ = enable, ’0’ = disable. 5 USB Speed ’0’ setup for full speed, ’1’ setup low speed. 4 J-K state force See Ta
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SL811HS Interrupt Enable Register [Address = 06h]. The SL811HS routed to the INTRQ pin. The Interrupt Status register is provides an Interrupt Request Output, which is activated for a normally used in conjunction with the Interrupt Enable register number of conditions. The Interrupt Enable register allows the and can be polled in order to determine the conditions that user to select conditions that result in an interrupt that is issued initiated the interrupt (See the description for the Inter
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SL811HS Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing interrupt status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register is written with corre- sponding bit set to ’1’. Table 14. Interrupt Status Register [Address 0Dh] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D+ Device Insert/Remove SOF timer Reserved Reserved USB-B USB-A Detect/Resume Bit Position Bit Name Function 7
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SL811HS Table 16. SOF Counter LOW Address when Written [Address 0Eh] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h. SOF Counter High/Control Register 2 [Address = 0Fh]. When read, this register returns the value of the SOF counter divided by 64. The software must use this register to determine the available bandwidth in the current frame before initiating any USB tr
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SL811HS SL811HS Slave Mode Registers Table 19. SL811HS Slave/Peripheral Mode Register Summary Endpoint specific register addresses Register Name EP 0 – A EP 0 - B EP 1 – A EP 1 - B EP 2 - A EP 2 - B EP 3 - A EP 3 - B EP Control Register 00h 08h 10h 18h 20h 28h 30h 0x38 EP Base Address Register 01h 09h 11h 19h 21h 29h 31h 0x39 EP Base Length Register 02h 0Ah 12h 1Ah 22h 2Ah 0x32 0x3A EP Packet Status Register 03h 0Bh 13h 1Bh 23h 2Bh 0x33 0x3B EP Transfer Count Register 04h 0Ch 14h 1Ch 24h 2Ch
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SL811HS Endpoint Control Registers Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Each endpoint set has a Control register defined as follows: Table 22. Endpoint Control Register [Address EP0a/b:00h/08h, EP1a/b:10h/18h, EP2a/b:20h/28h, EP3a/b:30h/38h] 7 6 5 4 3 2 1 0 Reserved Sequence Send STALL ISO Next Data Set Direction Enable Arm Bit Position Bit Name Function 7 Reserved 6 Sequence Sequence bit. '0' if DATA0, '1' if DATA1. 5 Send STALL When set to ‘1’, sends S
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SL811HS Endpoint Packet Status [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]. The packet status contains information relative to the packet that is received or transmitted. The register is defined as follows: Table 25. Endpoint Packet Status Reg [Address EP0a/b:03h/0Bh, EP1a/b:13h/1Bh, EP2a/b:23h/2Bh, EP3a/b:33h/3Bh] 7 6 5 4 3 2 1 0 Reserved Reserved Overflow Setup Sequence Time-out Error ACK Bit Position Bit Name Function 7 Reserved Not applicable. 6 Reserved Not applicable. 5 Overflow O
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SL811HS Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control bits. Table 28. Control Register 1 [Address 05h] 7 6 5 4 3 2 1 0 Reserved STBYD SPSEL J-K1 J-K0 DMA Dir DMA Enable USB Enable Bit Position Bit Name Function 7 Reserved Reserved bit - must be set to '0'. 6 STBYD XCVR Power Control. ‘1’ sets XCVR to low power. For normal operation set this bit to ‘0’. Suspend mode is entered if bit 6 = ‘1’ and bit ‘0’ (USB Enable)
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SL811HS Interrupt Enable Register, Address [06h] . The SL811HS initiated the interrupt (see the description in section Interrupt provides an Interrupt Request Output that is activated Status Register, Address [0Dh]). When a bit is set to ‘1’, the resulting from a number of conditions. The Interrupt Enable corresponding interrupt is enabled. Setting a bit in the Interrupt register allows the user to select events that generate the Enable register does not effect the Interrupt Status register’s
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SL811HS Current Data Set Register, Address [0Eh]. This register indicates current selected data set for each endpoint. Table 33. Current Data Set Register [Address 0Eh] 7 6 5 4 3 2 1 0 Reserved Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 Bit Position Bit Name Function 7-4 Reserved Not applicable. 3 Endpoint 3 Done Endpoint 3a = 0, Endpoint 3b = 1. 2 Endpoint 2 Done Endpoint 2a = 0, Endpoint 2b = 1. 1 Endpoint 1 Done Endpoint 1a = 0, Endpoint 1b = 1. 0 Endpoint 0 Done Endpoint 0a = 0, Endpo
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SL811HS Physical Connections These parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are the SL811HS and SL811HS-JCT. The 48-pin TQFP packages is the SL811HST-AXC. 28-Pin PLCC Physical Connections 28-Pin PLCC Pin Layout *See Table 35 on page 21 for Pin and Signal Description for Pins 2 and 3 in Host Mode. Figure 4. 28-pin PLCC USB Host/Slave Controller — Pin Layout nRD nDACK* VDD1 A0 M/S D7 nDRQ* 26 4 3 27 2 1 28 D6 nWR 25 5 D5 nCS 24 6 23 C
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SL811HS The diagram below illustrates a simple +3.3V voltage source. Figure 5. Sample VDD Generator +5V (USB) R1 45 Ohms 2N2222 Zener +3.3 V (VDD) 3.9v, 1N52288CT- GND Sample VDD Generator Package Markings (28-pin PLCC) Part Number YYWW-X.X XXXX YYWW = Date code XXXX = Product code X.X = Silicon revision number Document 38-08008 Rev. *D Page 19 of 32
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SL811HS 48-Pin TQFP Physical Connections 48-Pin TQFP AXC Pin Layout Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout NC nRD nDACK* D7 NC VDD [4] nDRQ* NC NC NC A0 M/S 37 1 36 48 NC NC NC NC nWR NC nCS D6 CM D5 D4 VDD1 48-Pin TQFP Data+ GND Data- D3 USBGnd D2 NC D1 NC NC NC 12 24 NC 25 13 nRST GND NC NC NC Clk/X1 NC NC VDD D0 INTRQ X2 *See Table 35 on page 21 for Pin and Signal Description for Pins 43 and 44 in Host Mode. 48-Pin TQFP Mechanical Dimens
