Résumé du contenu de la page N° 1
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Features Functional Description
[1]
■ Supports bus operation up to 250 MHz The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells
■ Available speed grades are 250, 200, and 167 MHz
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
■ Registered inputs and outputs for pipelined operation
g
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [3] Logic Block Diagram – CY7C1380D/CY7C1380F (512K x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV Q1 BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQ D , DQP D DQ D ,DQP D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ C , DQP C DQ C , DQP C BYTE BYTE BW C OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQP A DQ B , DQP B E DQ B , DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQ A , DQP A D
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(512K X 36) Figure 2. CY7C1382D, CY7C1382F (1M X 18) Document #: 38-05543 Rev. *F Page 3 of 34 [+] Feedback
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 119-Ball BGA Pinout Figure 3. CY7C1380F (512K X 36) 1 23 4 5 6 7 A V AA A A V ADSP DDQ DDQ B NC/288M AA ADSC A A NC/576M C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V CE V DQ DQ C C SS 1 SS B B F V DQ V V DQ V DDQ C SS OE SS B DDQ G DQ DQ BW BW DQ DQ ADV C C C B B B H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC DQ DQ BW D D A A D A M V DQ V V DQ V BWE
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 165-Ball FBGA Pinout (3-Chip Enable) Figure 5. CY7C1380D/CY7C1380F (512K x 36) 1 234 5 6 7 89 10 11 A NC/288M CE BW BW CE ADSC A NC A BWE ADV 1 C B 3 B NC/144M A CE2 BW BW CLK GW OE ADSP A NC/576M D A DQP NC V V V V V V V NC/1G DQP C C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 1. Pin Definitions Name I/O Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the rising edge of 0 1 [2] Synchronous the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A1: A0 1 2 3 are fed to the two-bit counter. . BW , BW Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. A B BW , BW Synchronous Sampled on the rising
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 1. Pin Definitions (continued) MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V or left DD floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG output feature is not being utilized, this pin mu
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Single Write Accesses Initiated by ADSP Functional Overview This access is initiated when both the following conditions are All synchronous inputs pass through input registers controlled by satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE , 1 the rising edge of the clock. All data outputs pass through output CE , and CE are all asserted active. The address presented to 2 3 registers controlled by the rising edge of the clock. Maximum A is loa
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 2. Interleaved Burst Address Table (MODE = Floating Burst Sequences or VDD) The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F First Second Third Fourth provides a two-bit wraparound counter, fed by A1: A0, that imple- Address Address Address Address ments an interleaved or a linear burst sequence. The interleaved A1: A0 A1: A0 A1: A0 A1: A0 burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is desig
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Truth Table [4, 5, 6, 7, 8] The Truth Table for this data sheet follows. Operation Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-Sta
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [4, 9] Truth Table for Read/Write Function (CY7C1380D/CY7C1380F) GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – (DQ and DQP) H L HHH L A A Write Byte B – (DQ and DQP)H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP) H LH LH H C C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQ and DQP) H L L HHH D D Write Bytes D, A H L L H H L Write Bytes D, B H L
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the registers The CY7C1380D/CY7C1382D incorporates a serial boundary and can be connected to the input of any of the registers. The scan test access port (TAP).This part is fully compliant with register between TDI and TDO is chosen by the instruction that 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V is loaded into the TAP inst
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F When the TAP controller is in the Capture-IR state, the two least the IDCODE to be shifted out of the device when the TAP significant bits are loaded with a binary ‘01’ pattern to enable fault controller enters the Shift-DR state. isolation of the board-level serial test data path. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test Bypass Register logic reset state. To save time whe
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F when the EXTEST is entered as the current instruction. When output Q-bus pins. Note that this bit is preset HIGH to enable the HIGH, it enables the output buffers to drive the output bus. When output when the device is powered up, and also when the TAP LOW, this bit places the output bus into a High-Z condition. controller is in the Test-Logic-Reset state. This bit can be set by entering the SAMPLE/PRELOAD or Reserved EXTEST command, and then shifting t
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels.................................................V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times....................................................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels................... ........................1.5V
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Identification Register Definitions CY7C1380D/CY7C1380F CY7C1382D/CY7C1382F Instruction Field Description (512K x 36) (1 Mbit x 18) Revision Number (31:29) 000 000 Describes the version number. [13] Device Depth (28:24) 01011 01011 Reserved for internal use. Device Width (23:18) 119-BGA 101000 101000 Defines the memory type and architecture. Device Width (23:18) 165-FBGA 000000 000000 Defines the memory type and architecture. Cypress Device ID (17:12)
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [14, 15] 119-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 23 F6 45 G4 67 L1 H4 2 T4 24 E746 A468 M2 3T5 25 D7 47 G3 69 N1 4 T6 26 H748 C370 P1 5R5 27 G6 49 B2 71 K1 6 L5 28 E650 B372 L2 7 R629 D651 A3 73 N2 8 U630 C752 C274 P2 9 R7 31 B753 A275 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [14, 16] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N7 32 C11 62 D2 3 N10 33 A11 63 E2 4P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA Exceeding the maximum ratings may impair the useful life of the Static Discharge Voltage........................................... >2001V device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Cur
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [19] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package C Input Capacitance T = 25°C, f = 1 MHz, 58 9 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 8 9 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 8 9 pF IO [19] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package Θ Thermal Resistance Test conditions follow standard 28.66 23.8 20.7 °
