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CY7C1470V33
CY7C1472V33
CY7C1474V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
• Pin-compatible and functionally equivalent to ZBT™
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
• Supports 250-MHz bus operations with zero wait states
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
— Available speed grades
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Logic Block Diagram-CY7C1472V33 (4M x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E A U ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY WRITE DQs BWa E ARRAY S U CONTROL LOGIC G DRIVERS A F T DQPa I BWb M E F S DQPb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations 100-pin TQFP Packages DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V 4 V DDQ 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 SS 71 V V DDQ DDQ 11 V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS 67 SS V V DD 15 NC DD 15 NC 66
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470V33 (2M x 36) 1 234 5 6 7 89 10 11 NC/576M A A A NC A CE ADV/LD CE BW BW CEN 3 1 c b B NC/1G A CE2 BW BW CLK WE OE A A NC d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS SS SS DDQ b D DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ E c c DD SS SS DD b b DDQ SS DDQ F DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b G DQ DQ V V V V V V V
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474V33 (1M x 72) 12 3 4 5 6 7 8 9 10 11 A DQg DQgAA CE ADV/LDA CEA DQb DQb 2 3 DQg DQg BWS BWS NC WE A BWS BWS DQb DQb B c g b f DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb C h d 1 e a D DQg NC DQg V NC/1G OE NC V SS NC DQb SS DQb E DQPg DQPc V V V V V V V DDQ DDQ DD DD DD DDQ DDQ DQPf DQPb F DQc DQc V V V V NC V V DQf SS SS SS SS SS SS DQf G DQc V DQc V V V NC DD V V DDQ DDQ DQf
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Definitions Pin Name I/O Type Pin Description A0 Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of A1 Synchronous the CLK. A BW Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. a BW Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , b a a a b b b BW BW controls DQ and DQP , BW controls DQ and DQP , BW controls DQ
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Definitions (continued) Pin Name I/O Type Pin Description TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG Clock Clock input to the JTAG circuitry. V Power Supply Power supply inputs to the core of the device. DD V I/O Power Supply Power supply for the I/O circuitry. DDQ V Ground Ground for the device. Should be connected to ground of the system. SS NC – No connects. Th
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CY7C1470V33 CY7C1472V33 CY7C1474V33 On the next clock rise the data presented to DQ and DQP CY7C1474V33, BW for CY7C1470V33 and BW for a,b,c,d a,b (DQ /DQP for CY7C1474V33, CY7C1472V33) inputs must be driven in each cycle of the a,b,c,d,e,f,g,h a,b,c,d,e,f,g,h DQ /DQP for CY7C1470V33 & DQ /DQP for burst write in order to write the correct bytes of data. a,b,c,d a,b,c,d a,b a,b CY7C1472V33) (or a subset for byte write operations, see Sleep Mode Write Cycle Description table for details) input
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CY7C1470V33 CY7C1472V33 CY7C1474V33 [1, 2, 3, 4, 5, 6, 7] Truth Table Operation Address Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Deselect Cycle None H L L X X X L L-H Tri-State Continue None X L H X X X L L-H Tri-State Deselect Cycle Read Cycle External L L L H X L L L-H Data Out (Q) (Begin Burst) Read Cycle Next X L H X X L L L-H Data Out (Q) (Continue Burst) NOP/Dummy Read External L L L H X H L L-H Tri-State (Begin Burst) Dummy Read Next X L H X X H L L-H Tri-State (Continue Burst) Write Cyc
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CY7C1470V33 CY7C1472V33 CY7C1474V33 [1, 2, 3, 8] Partial Write Cycle Description Function (CY7C1470V33) WE BW BW BW BW d c b a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ and DQP) L HHH L a a Write Byte b – (DQ and DQP)LHHLH b b Write Bytes b, a L H H L L Write Byte c – (DQ and DQP)LHLHH c c Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQ and DQP)LLHHH d d Write Bytes d, a L L H H L Write Bytes d, b L LHLH Write
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1470V33, CY7C1472V33, and CY7C1474V33 and is sampled on the rising edge of TCK. It is allowable to incorporates a serial boundary scan test access port (TAP). leave this ball unconnected if the TAP is not used. The ball is This port operates in accordance with IEEE Standard pulled up internally, resulting in a logic HIGH level.
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Instruction Register Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between Three-bit instructions can be serially loaded into the instruction TDI and TDO. During this state, instructions are shifted register. This register is loaded when it is placed between the through the instruction register through the TDI and TDO balls. TDI and TDO balls as shown in the Tap Controller Block To execute t
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CY7C1470V33 CY7C1472V33 CY7C1474V33 possible to capture all other signals and simply ignore the BYPASS value of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction Once the data is captured, it is possible to shift out the data by register and the TAP is placed in a Shift-DR state, the bypass putting the TAP into the Shift-DR state. This places the register is placed between the TDI and TDO balls. The boundary scan register between the TDI a
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CY7C1470V33 CY7C1472V33 CY7C1474V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Inp
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Identification Register Definitions CY7C1470V33 CY7C1472V33 CY7C1474V33 Instruction Field (2M x 36) (4M x 18) (1M x 72) Description Revision Number (31:29) 000 000 000 Describes the version number [12] Device Depth (28:24) 01011 01011 01011 Reserved for internal use Architecture/Memory 001000 001000 001000 Defines memory type and archi- Type(23:18) tecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density Cypress JEDEC ID Code 000001101
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3E1 23 R4 43 J10 63 A6 4D2 24 P6 44 H11 64 B5 5E2 25 R6 45 G11 65 A5 6F1 26 R8 46 F11 66 A4 7G1 27 P3 47 E11 67 B4 8F2 28 P4 48 D10 68 B3 9G2 29 P8 49D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2A2 30 T2 58 T11 86 B10 3B1 31 U1 59 T10 87 A11 4B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71
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CY7C1470V33 CY7C1472V33 CY7C1474V33 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature
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CY7C1470V33 CY7C1472V33 CY7C1474V33 [15] Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Address Input Capacitance T = 25°C, f = 1 MHz, 6 6 6 pF ADDRESS A V = 3.3V DD C Data Input Capacitance 5 5 5 pF DATA V = 2.5V DDQ C Control Input Capacitance 8 8 8 pF CTRL C Clock Input Capacitance 6 6 6 pF CLK C Input/Output Capacitance 5 5 5 pF I/O [15] Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Parameters Description Test Conditions Package Packa
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CY7C1470V33 CY7C1472V33 CY7C1474V33 [16, 17] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max. Min. Max. Min. Max. Unit [18] t V (typical) to the First Access Read or Write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC F Maximum Operating Frequency 250 200 167 MHz MAX t Clock HIGH 2.0 2.0 2.2 ns CH t Clock LOW 2.0 2.0 2.2 ns CL Output Times t Data Output Valid After CLK Rise 3.0 3.0 3.4 ns CO t OE LOW to Output Valid 3.0 3.0 3.4
