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® CY62138FV30 MoBL Package Diagrams (continued) Figure 5. 32-pin STSOP (8 x 13.4 mm), 51-85094 51-85094-*D MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-08029 Rev. *E Page 12 of 13 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation
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® CY62138FV30 MoBL Document History Page ® Document Title: CY62138FV30 MoBL , 2-Mbit (256K x 8) Static RAM Document Number: 001-08029 Issue Orig. of REV. ECN NO. Description of Change Date Change ** 463660 See ECN NXR New data sheet *A 467351 See ECN NXR Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages Changed ball A3 from NC to CE in 36-ball FBGA pin out 2 *B 566724 See ECN NXR Converted from Preliminary to Final Corrected typo in 32 pin TSOP II pin configuration diagram
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®
CY62138FV30 MoBL
2-Mbit (256K x 8) Static RAM
[1]
Features Functional Description
• Very high speed: 45 ns The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
• Wide voltage range: 2.20V–3.60V
advanced circuit design to provide ultra low active current.
• Pin compatible with CY62138CV25/30/33 ®
This is ideal for providing More Battery Life™ (MoBL ) in
• Ultra low standby power
portable applications such as cellular telephones. The devi
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® CY62138FV30 MoBL [2] Pin Configuration 36-Ball VFBGA Top View 32-Pin SOIC/TSOP II Top View A A A A A CE 3 6 8 A V 0 1 2 A 1 CC 17 32 A A 16 2 31 15 A CE 14 3 30 2 A IO WE A IO B A 4 4 7 0 2 A 12 4 29 WE A 7 5 A 28 13 A A NC A C 6 IO IO 6 27 8 5 5 1 A A 5 7 26 9 A A 4 8 25 11 V V A SS CC D 3 9 24 OE A 2 10 A 23 10 A 1 11 22 CE V 1 V SS E CC A 0 12 21 IO 7 IO 0 13 20 IO 6 IO 1 14 IO 19 NC F 5 IO A IO 17 6 2 IO 2 15 18 IO 4 V 16 17 IO SS 3 CE A IO G OE 1 A IO 16 7 15 3 A A A A A A 10 11 12 13 H
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® CY62138FV30 MoBL [4, 5] DC Input Voltage .......................................–0.3V to 3.9V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage.......................................... > 2001V device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ..................................–65°C to +150°C Latch-up Current ........................
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® CY62138FV30 MoBL [8] Thermal Resistance Parameter Description Test Conditions SOIC VFBGA TSOP II STSOP TSOP I Unit Θ Thermal Resistance Still air, soldered on a 3 x 4.5 44.53 38.49 44.16 59.72 50.19 °C/W JA (Junction to Ambient) inch, two layer printed circuit board Θ Thermal Resistance 24.05 17.66 11.97 15.38 14.59 °C/W JC (Junction to Case) AC Test Loads and Waveforms R1 ALL INPUT PULSES V CC OUTPUT V CC 90% 90% 10% 10% R2 GND 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING JIG AND E
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® CY62138FV30 MoBL [11] Switching Characteristics (Over the Operating Range) 45 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 ns ACE 1 2 t OE LOW to Data Valid 22 ns DOE [12] t OE LOW to Low-Z 5ns LZOE [12,13] t OE HIGH to High-Z 18 ns HZOE [12] t CE LOW and CE HIGH to Low Z 10 ns LZCE 1 2 [12, 13] t CE HIGH or CE LOW to High-Z 18 ns HZCE 1 2 t CE LOW
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® CY62138FV30 MoBL Switching Waveforms [15, 16] Read Cycle 1 (Address transition controlled) tRC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [10, 16, 17] Read Cycle No. 2 (OE controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT t LZCE t PD I t V CC PU CC SUPPLY 50% 50% CURRENT I SB [10, 14, 18, 19] Write Cycle No. 1 (WE controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t HD DATA IO NOTE 20 DATA VAL
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® CY62138FV30 MoBL Switching Waveforms (continued) [10, 14, 18, 19] Write Cycle No. 2 (CE1 or CE2 controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t t SD HD DATA IO DATA VALID [10, 19] Write Cycle No. 3 (WE controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 20 DATA VALID DATA IO t t LZWE HZWE Truth Table CE CE WE OE Inputs/Outputs Mode Power 1 2 H X X X High-Z Deselect/Power Down Standby (I ) SB X L X X High-Z Deselect/Power Down Standby (I ) SB L H H L D
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® CY62138FV30 MoBL Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY62138FV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free) Industrial CY62138FV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free) CY62138FV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) CY62138FV30LL-45ZXI 51-85056 32-pin TSOP I (Pb-free) CY62138FV30LL-45SXI 51-85081 32-pin SOIC (Pb-free) Package Diagrams Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.
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® CY62138FV30 MoBL Package Diagrams (continued) Figure 2. 32-pin TSOP II, 51-85095 51-85095-** Document #: 001-08029 Rev. *E Page 9 of 13 [+] Feedback
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® CY62138FV30 MoBL Package Diagrams (continued) Figure 3. 32-pin (450 Mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.006[0.152] 0.817[20.751] 0.012[0.304] 0.101[2.565] 0.118[2.997] 0.111[2.819] MAX. 0.004[0.102] 0.047[1.193] 0.004[0.102] 0.063[1.600] 0.050[1.270] MIN. 0.023[0.584] BSC. 0.039[0.990] 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B Document #: 001-08029 Rev. *E Page 10 of 13 [+] Feedback
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® CY62138FV30 MoBL Package Diagrams (continued) Figure 4. 32-pin TSOP I (8 x 20 mm), 51-85056 51-85056-*D Document #: 001-08029 Rev. *E Page 11 of 13 [+] Feedback
