Résumé du contenu de la page N° 1
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Features Functional Description
■ True Dual-Ported Memory Cells that Allow Simultaneous The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
Access of the Same Memory Location and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
■ Synchronous Pipelined Operation
provided, permitting i
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [2] Logic Block Diagram OE OE L R R/W R/W L R B0 B0 L R B1 B1 L R CE CE 0L 0R CE CE 1L 1R I/O I/O 9 9 DQ –DQ Control Control DQ –DQ 9L 17L 9R 17R 9 9 DQ –DQ DQ –DQ 0L 8L 0R 8R Addr. Addr. Read Read True Back Back Dual-Ported RAM Array 19 19 A –A A –A 0L 18L 0R 18R Mask Register Mask Register CNT/MSK CNT/MSK R L ADS ADS Counter/ Counter/ L Address Address Address Address CNTEN CNTEN L Register Register Decode Decode CNTR
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Configurations Figure 1. 144-Ball BGA (Top View) CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV 1 2 3 4 5 6 7 8 9 10 11 12 A DQ17 DQ16 DQ14 DQ12 DQ10 DQ9 DQ9 DQ10 DQ12 DQ14 DQ16 DQ17 L L L L L L R R R R R R B A0 A1 DQ15 DQ13 DQ11 MRST NC DQ11 DQ13 DQ15 A1 A0 L L L L L R R R R R CE1 CNTINT ADS ADS CNTINT CE1 L L R R L R C A2 A3 INT INT A3 A2 L L L [9] [9] R R R [7] [8] [8] [7] CE0 CE0 L R D A4 A5 NC VDD VD
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Configurations Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (Top View) CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV A 90 2L 1 A 2R A 3L 89 2 A 3R V 88 SS 3 V SS V 87 DD 4 V DD A 4L 86 5 A 4R A 85 5L 6 A 5R A 6L 84 7 A 6R A 83 7L 8 A 7R CE 1L 82 9 CE 1R B 81 0L 10 B 0R B 1L 11 80 B 1R OE 79 L 12 OE R CE 0L 78 13 CE 0R V DD 14 77 V DD V 76 SS 15 V SS R/W 75 L 16 R/W R CLK L 74 17 CLK R V SS 18 73 MRST ADS L 72 19 ADS
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Definitions Left Port Right Port Description [2] [2] A –A A –A Address Inputs. 0L 18L 0R 18R [8] [8] ADS ADS Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for L R the part using the externally supplied address on the address pins and for loading this address into the burst address counter. [8] [8] CE0 CE0 Active LOW Chip Enable Input. L R [7] [7] CE1 CE1 Active HIGH Chip Enable
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV The counter register contains the address used to access the Master Reset RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The FLEx18 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchro- The mask register value affects the Increment and Counter nously to the clocks. An MRST initializes the internal burst Res
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV address counter is then loaded with an initial value of 8h. The Counter Reset Operation base address bits (in this case, the 6th address through the 16th All unmasked bits of the counter are reset to ‘0.’ All masked bits address) are loaded with an address value but do not increment remain unchanged. The mirror register is loaded with the value after the counter is configured for increment operation. The of the burst counter.
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Retransmit Mask Readback Operation Retransmit is a feature that allows the Read of a block of memory The internal value of the mask register can be read out on the more than once without the need to reload the initial address. address lines. Readback is pipelined; the address is valid t CM2 This eliminates the need for external logic to store and route after the next rising edge of the port’s clock. If mask readback data. It
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [1] Figure 3. Counter, Mask, and Mirror Logic Block Diagram CNT/MSK CNTEN Decode ADS Logic CNTRST MRST Bidirectional Mask Address Register Lines Counter/ Address RAM Address Decode Array Register CLK Load/Increment From 17 Address Mirror Counter Lines To Readback 1 1 and Address 0 Decode 0 From 17 Increment Mask Logic 17 Wrap Register 17 17 From Mask Bit 0 17 From +1 Wrap Counter Wrap 1 Detect 0 +2 17 1 To Counter
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV [2, 20] Figure 4. Programmable Counter-Mask Register Operation CNTINT Example: Load Counter-Mask H 0 0 0s01 11 1 1 1 Register = 3F 16 15 6 5 4 3 2 1 0 Mask 2 2 2 2 2 2 2 2 2 Register Masked Address Unmasked Address bit-0 Load Address H X X Xs X0 00 1 0 0 Counter = 8 16 15 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 Address Counter Max bit-0 Address L X X Xs X1 11 1 1 1 Register 16 15 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 Max + 1 Address H X
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 5. Scan Chain for 9 Mb Device TDO TDO D2 TDI TDO D1 TDI TDI Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 0h Reserved for version number. Cypress Device ID (27:12) C090h Defines Cypress part number for CY7C0832AV/CY7C0832BV C091h Defines Cypress part number for CY7C0831AV C093h Defines Cypress part number for CY7C0830AV C094h Defines Cypress part number for
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage........................................... > 2000V [23] Exceeding maximum ratings may impair the useful life of the (JEDEC JESD22-A114-2000B) device. These user guidelines are not tested. Latch Up Current .................................................... > 200 mA Storage Temperature................................
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 6. AC Test Load and Waveforms 3.3V Z = 50 Ω R = 50 Ω 0 OUTPUT R1 = 590 Ω OUTPUT C = 10 pF C = 5 pF V = 1.5V R2 = 435 Ω TH (a) Normal Load (Load 1) (b) Three-state Delay (Load 2) 3.0V 90% 90% 10% 10% ALL INPUT PULSES Vss < 2ns < 2ns Switching Characteristics Over the Operating Range -167 -133 -100 CY7C0837AV CY7C0837AV CY7C0830AV CY7C0830AV Parameter Description CY7C0831AV CY7C0833AV CY7C0833AV Unit CY7C0831AV CY7C083
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Characteristics (continued) Over the Operating Range -167 -133 -100 CY7C0837AV CY7C0837AV CY7C0830AV CY7C0830AV Parameter Description CY7C0831AV CY7C0833AV CY7C0833AV Unit CY7C0831AV CY7C0832AV CY7C0832AV CY7C0832BV Min Max Min Max Min Max Min Max t CNT/MSK Hold Time 0.6 0.6 NA NA ns HCM t Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns OE [28,29] t OE to Low Z 0 0 ns OLZ [28,29] t OE to High Z 0 4.0 0 4.4 4.7 5.0 n
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV JTAG Timing and Switching Waveforms CY7C0837AV/CY7C0830AV CY7C0831AV/CY7C0832AV Parameter Description Unit CY7C0832BV/CY7C0833AV Min Max f Maximum JTAG TAP Controller Frequency 10 MHz JTAG t TCK Clock Cycle Time 100 ns TCYC t TCK Clock HIGH Time 40 ns TH t TCK Clock LOW Time 40 ns TL t TMS Setup to TCK Clock Rise 10 ns TMSS t TMS Hold After TCK Clock Rise 10 ns TMSH t TDI Setup to TCK Clock Rise 10 ns TDIS t TDI Hold After TC
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms Figure 8. Master Reset t RS MRST t ALL RSF ADDRESS/ DATA t LINES RSS t RSR ALL INACTIVE OTHER ACTIVE INPUTS TMS CNTINT INT TDO [12, 30, 31, 32, 33] Figure 9. Read Cycle t CYC2 t t CH2 CL2 CLK CE t t t t SC HC SC HC t SB t HB BE0–BE1 R/W t t SW HW t t SA HA ADDRESS A A A A n n+1 n+2 n+3 t 1 Latency t DC CD2 DATA OUT Q Q Q n n+1 n+2 t OHZ t t CKLZ OLZ OE t OE Notes 30. OE is asynchronously controlled; a
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) [34, 35] Figure 10. Bank Select Read t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A A A A A (B1) 0 A 3 4 5 1 2 t t HC SC CE (B1) t t t t t t CD2 t CD2 CD2 CKHZ HC CKHZ SC Q Q Q 3 DATA 0 1 OUT(B1) t t HA SA t t t DC DC CKLZ ADDRESS A A A A A A (B2) 0 3 4 5 1 2 t t SC HC CE (B2) t t t t CD2 CKHZ CD2 t SC HC DATA OUT(B2) Q Q 4 2 t t CKLZ CKLZ [33, 36, 37, 38, 39] Figure 11. Read-to-Write-to-Read (
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) [33, 36, 38, 39] Figure 12. Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK CE t t SC HC t t SW HW R/W t t SW HW A A A A A A n n+1 n+2 n+3 n+4 n+5 ADDRESS t t t t SA HA SD HD D DATA D n+2 IN n+3 t CD2 t CD2 DATA OUT Q Q n n+4 t OHZ OE READ WRITE READ [38] Figure 13. Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A n t t SAD HAD ADS t t SAD HAD CNTEN t
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) [39] Figure 14. Write with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA A ADDRESS n INTERNAL A A A A A n n+1 n+2 n+3 n+4 ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D D D D D D DATA n n+1 n+1 n+2 n+3 n+4 IN t t SD HD WRITE EXTERNAL WRITE WITH WRITE COUNTER WRITE WITH COUNTER ADDRESS COUNTER HOLD [40, 41] Figure 15. Counter Reset t CYC2 t t CH2 CL2 CLK t t SA HA A A A ADDRESS n m p
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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) [43, 44, 45, 46] Figure 16. Readback State of Address Counter or Mask Register t CYC2 t t CH2 CL2 CLK t or t t t CA2 CM2 SA HA EXTERNAL A ADDRESS A n* n A –A 0 16 INTERNAL A A ADDRESS A A A n+4 n n+1 n+2 n+3 t t SAD HAD ADS t t SCN HCN CNTEN t t t CD2 CKHZ CKLZ DATA OUT Q Q Q Q Q Q n+1 x-2 x-1 n n+2 n+3 LOAD READBACK INCREMENT EXTERNAL COUNTER ADDRESS INTERNAL ADDRESS Notes 43. CE = OE
