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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
®
PSoC Programmable System-on-Chip™
■ Versatile Analog Mux
Features
❐ Common Internal Analog Bus
■ Powerful Harvard Architecture Processor
❐ Simultaneous Connection of IO Combinations
❐ M8C Processor Speeds to 24 MHz
❐ Capacitive Sensing Application Capability
❐ Low power at high speed
■ Additional System Resources
❐ 2.4V to 5.25V Operating Voltage
2
❐ I C Master, Slave and Multi-Master to 400 kHz
❐ Operating Voltages Down to 1.0V using On-Ch
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Row Output Configuration Digital Clocks From Core CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 The Digital System PSoC Functional Overview The Digital System consists of 4 digital PSoC blocks. Each block The PSoC family consists of many Mixed-Signal Array with is an 8-bit resource that is used alone or combined with other On-Chip Controller devices. These devices are designed to blocks to form 8, 16, 24, and 32-bit peripherals, which are called replace multiple traditional MCU-based syst
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 The Analog Multiplexer System The Analog System The Analog Mux Bus can connect to every GPIO pin. Pins may The Analog System consists of 4 configurable blocks that allow be connected to the bus individually or in any combination. The the creation of complex analog signal flows. Analog peripherals bus also connects to the analog system for analysis with are very flexible and may be customized to support specific comparators and analog-to-digita
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 For up-to-date ordering, packaging, and electrical specification PSoC Device Characteristics information, see the latest PSoC device data sheets on the web Depending on your PSoC device characteristics, the digital and at www.cypress.com/psoc. analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific Application Notes PSoC device groups. The PSoC device covered by this
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Code Generation Tools Development Tools PSoC Designer supports multiple third party C compilers and ® PSoC Designer is a Microsoft Windows-based, integrated assemblers. The code generation tools work seamlessly within development environment for the Programmable the PSoC Designer interface and have been tested with a full System-on-Chip (PSoC) devices. The PSoC Designer IDE runs range of debugging tools. The choice is yours. on Windows XP or W
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 property, and other information you may need to successfully Designing with PSoC Designer implement your design. The development process for the PSoC device differs from that Organize and Connect of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a You can build signal chains at the chip level by interconnecting unique flexibility that pays dividends in managing specif
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Units of Measure Document Conventions A units of measure table is located in the Electrical Specifications Acronyms Used section. Table 2 on page 7 lists all the abbreviations used to measure the PSoC devices. The following table lists the acronyms that are used in this document. Numeric Naming Table 2. Acronyms Used Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or Acrony
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Pin Information The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 16-Pin Part Pinout Figure 3. CY8C21234 16-Pin PSoC Device A, I, M, P0[7] Vdd 1 16 A, I, M, P0[5] P0[6], A, I, M 2 15 A, I, M, P0[3] P0[4], A, I, M 3 14 A,
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 20-Pin Part Pinout Figure 4. CY8C21334 20-Pin PSoC Device A, I, M, P0[7] 20 Vdd 1 A, I, M, P0[5] P0[6], A, I, M 19 2 A, I, M, P0[3] P0[4], A, I, M 3 18 A, I, M, P0[1] 17 P0[2], A, I, M 4 Vss P0[0], A, I, M 16 5 SSOP M , I 2 C SC L , P1 [ 7 ] XRES 6 15 M, I 2 C SDA, P1 [5 ] 7 14 P 1 [6 ], M M, P 1 [ 3 ] P1[4 ], EXTCLK, M 8 13 M, I 2 C SCL ,P1 [1 ] 12 P 1 [2 ], M 9 Vss 10 11 P 1 [0 ], I2 C S D A , M Table 4. Pin Definitions - CY8C21334 20
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 28-Pin Part Pinout Figure 5. CY8C21534 28-Pin PSoC Device A, I, M, P0[7] 1 Vdd 28 A, I, M, P0[5] P0[6], A, I, M 2 27 A, I, M, P0[3] 3 26 P0[4], A, I, M A, I, M, P0[1] P0[2], A, I, M 4 25 M, P 2 [ 7 ] P0[0], A, I, M 5 24 M, P 2 [ 5 ] P 2 [ 6 ], M 6 23 M, P2[3] P 2 [ 4 ], M 7 22 SSOP M, P2[1] P 2 [ 2 ], M 8 21 Vss 9 20 P 2 [ 0 ], M M, I 2 C S C L , P 1 [ 7 ] XRES 10 19 M, I2C SDA, P1[5] P 1 [ 6 ], M 11 18 M, P 1 [ 3 ] 12 17 P1[4], EXTCLK, M
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 32-Pin Part Pinout Figure 9. CY8C21634 32-Pin PSoC Device Figure 6. CY8C21434 32-Pin PSoC Device Figure 10. CY8C21434 32-Pin Sawn PSoC Device Figure 11. CY8C21634 32-Pin Sawn PSoC Device A, I, M, P0[1] 1 24 P0[0], A, I, M A, I, M, P0[1] 1 24 P0[0], A, I, M M, P2[7] M, P2[7] 2 23 P2[6], M 2 23 P2[6], M M, P2[5] 3 22 P2[4], M M, P2[5] 3 22 P2[4], M M, P2[3] 4 P2[2], M M, P2[3] 4 P2[2], M QFN 21 QFN 21 M, P2[1] M, P2[1] 5 20 P2[0], M 5 20 P2
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 [4] Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN) Type Pin Name Description No. Digital Analog 1 IO I, M P0[1] Analog column mux input, integrating input. 2 IO M P2[7] 3 IO M P2[5] 4 IO M P2[3] 5 IO M P2[1] 6 IO M P3[3] In CY8C21434 part. 6 Power SMP Switch Mode Pump (SMP) connection to required external components in CY8C21634 part. 7 IO M P3[1] In CY8C21434 part. 7 Power Vss Ground connection in CY8C21634 part. 8 IO M P1[7]
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 12. CY8C21001 56-Pin PSoC Device Vss 56 Vdd 1 2 55 AI, P0[7] P0[6], AI AI, P0[5] P0[4], AI 3 54 AI, P0[3] P0[2], AI 4 53 AI, P0[1] P0[0], AI 5 52 P2[6] P2[7] 51 6 P2[5] 7 50 P2[4] P2[3] P2[2] 8 49 P2[1] 9 48 P2[0] NC 10 NC 47 NC 11 46 NC NC 12 45 P3[2]
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued) Type Pin No. Pin Name Description Digital Analog 19 IO P3[3] 20 IO P3[1] 21 NC No connection. 22 NC No connection. 23 IO P1[7] I2C Serial Clock (SCL). 24 IO P1[5] I2C Serial Data (SDA). 25 NC No connection. 26 IO P1[3] I . FMTEST [3] 27 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK .. 28 Power Vss Ground connection. 29 NC No connection. 30 NC No connection. [
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Register Reference This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Programmable System-on-Chip Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 8. Table 8. Register Conventions Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 9. Register Map 0 Table: User Space (continued) DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW DBB00DR2 22 RW PWM_CR 62 RW A2 INT_VC E2 RC DBB00CR0 23 # 63 A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 E4 DBB01DR1 25 W 65 A5 E5 DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # ADC0_CR 68 # A8 E8 DCB02DR1 29 W ADC1_CR 69 # A9 E9 DCB02DR2 2A RW 6A AA
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 10. Register Map 1 Table: Configuration Space (continued) 15 55 95 D5 16 56 96 D6 17 57 97 D7 18 58 98 MUX_CR0 D8 RW 19 59 99 MUX_CR1 D9 RW 1A 5A 9A MUX_CR2 DA RW 1B 5B 9B MUX_CR3 DB RW 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW 23 AMD_CR0 63 RW A3 VLT_CR E3 RW DB
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Valid Operating Region CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up to date electrical specifications, visit the web site http://www.cypress.com/psoc. o o o Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C as specified, except where noted. A J Refer Table 25 on page 26 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mo
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Absolute Maximum Ratings Table 12. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes o T Storage Temperature -55 25 +100 C Higher storage temperatures STG reduce data retention time. Recom- mended storage temperature is o o +25 C ± 25 C. Extended duration o storage temperatures above 65 C degrade reliability. o T Ambient Temperature with Power Applied -40 – +85 C A Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 14. DC Chip-Level Specifications (continued) Symbol Description Min Typ Max Units Notes o o I Sleep (Mode) Current with POR, LVD, Sleep – 2.6 4. μA Vdd = 2.55V, 0 C ≤ T ≤ 40 C. SB27 A Timer, WDT, and internal slow oscillator active. Mid temperature range. o o I Sleep (Mode) Current with POR, LVD, Sleep – 2.8 5 μA Vdd = 3.3V, -40 C ≤ T ≤ 85 C. SB A Timer, WDT, and internal slow oscillator active. V Reference Voltage (Bandgap) 1.28 1.30
