Instruction d'utilisation Cypress CY7C185

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fax id: 1013
CY7C185
8K x 8 Static RAM
provided by an active LOW chip enable (CE ), an active HIGH
Features
1
chip enable (CE ), and active LOW output enable (OE) and
2
• High speed
three-state drivers. This device has an automatic power-down
feature (CE or CE ), reducing the power consumption by 70%
—15 ns 1 2
when deselected. The CY7C185 is in a standard 300-mil-wide
• Fast t
DOE
DIP, SOJ, or SOIC package.
• Low active power
An active LOW write enable signal (WE) controls the writ-
—715 mW
i

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CY7C185 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-Up Current.................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Operating Range Power Applied.................

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CY7C185 Electrical Characteristics Over the Operating Range (continued) 7C185–25 7C185-35 Parameter Description Test Conditions Min. Max. Min. Max. Unit V Output HIGH Voltage V = Min., I = –4.0 mA 2.4 2.4 V OH CC OH V Output LOW Voltage V = Min., I = 8.0 mA 0.4 0.4 V OL CC OL V Input HIGH Voltage 2.2 V + 2.2 V + V IH CC CC 0.3V 0.3V [2] V Input LOW Voltage –0.5 0.8 –0.5 0.8 V IL I Input Load Current GND ≤ V ≤ V –5 +5 –5 +5 μA IX I CC I Output Leakage GND ≤ V ≤ V , –5 +5 –5 +5 μA OZ I CC Current

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CY7C185 [5] Switching Characteristics Over the Operating Range 7C185–15 7C185–20 7C185–25 7C185–35 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE t Read Cycle Time 15 20 25 35 ns RC t Address to Data Valid 15 20 25 35 ns AA t Data Hold from 3 5 5 5 ns OHA Address Change t CE LOW to Data Valid 15 20 25 35 ns ACE1 1 t CE HIGH to Data Valid 15 20 25 35 ns ACE2 2 t OE LOW to Data Valid 8 9 12 15 ns DOE t OE LOW to Low Z 3 3 3 3 ns LZOE [6] t OE HIGH to High Z 7 8 10 10

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CY7C185 Switching Waveforms [9,10] Read Cycle No.1 t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID C185–6 [11,12] Read Cycle No.2 t RC CE 1 CE 2 t ACE OE OE t HZOE t DOE t HZCE t LZOE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT DATA VALID t LZCE t PD t PU V ICC CC SUPPLY 50% 50% CURRENT ISB C185–7 [10,12] Write Cycle No. 1 (WE Controlled) t WC ADDRESS CE t SCEI 1 t t AW HA t CE CE 2 SCE2 t t SA PWE WE OE t SD t HD DATA VALID NOTE 13 DATA I/O IN C185–8 t HZOE 9. Device is continuously

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CY7C185 Switching Waveforms (continued) [12,13,14] Write Cycle No. 2 (CE Controlled) t WC ADDRESS t CE SCE1 1 t SA t SCE2 CE 2 t t AW HA WE t t SD HD DATA VALID DATA I/O IN C185–9 [12,13,14,15] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t CE SCE1 1 CE t 2 SCE2 t t AW HA t SA WE t t SD HD DATA I/O DATA VALID NOTE 13 IN t t LZWE HZWE C185–10 Notes: 14. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t and t . HZWE SD 15. If CE goes HIGH or CE goes

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CY7C185 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 1.4 1.2 120 1.2 1.0 100 I I CC CC 1.0 0.8 80 0.8 V =5.0V CC 0.6 60 T =25°C A 0.6 0.4 40 V =5.0V CC 0.4 V =5.0V IN 0.2 20 0.2 I SB I SB 0 0.0 0.0 –55 25 125 0.0 1.0 2.0 3.0 4.0 4.0 4.5 5.0 5.5 6.0 AMBIENT TEMPERATURE ( C) ° OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CUR

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CY7C185 Truth Table CE CE WE OE Input/Output Mode 1 2 H X X X High Z Deselect/Power-Down X L X X High Z Deselect/Power-Down L H H L Data Out Read L H L X Data In Write L H H H High Z Deselect Address Designators Address Address Pin Name Function Number A4 X3 2 A5 X4 3 A6 X5 4 A7 X6 5 A8 X7 6 A9 Y1 7 A10 Y4 8 A11 Y3 9 A12 Y0 10 A0 Y2 21 A1 X0 23 A2 X1 24 A3 X2 25 Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 15 CY7C185–15PC P21 28-Lead (300-Mil) Molded DI

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CY7C185 Package Diagrams 28-Lead (300-Mil) Molded DIP P21 51-85014-B 28-Lead (300-Mil) Molded SOIC S21 51-85026-A 9

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CY7C185 Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 51-85031-B © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical compone