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CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18
• Available speed grades are 250, 200, and 167 MHz
SRAM cells with advanced synchronous peripheral circuitry
• Registered inputs and outputs for pipelined operation
and a two-bit counter for internal burst operation. All
synchronous
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 [3] Logic Block Diagram – CY7C1380DV25/CY7C1380FV25 (512K x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV Q1 BURST CLK COUNTER AND CLR Q0 LOGIC ADSC ADSP DQ D , DQP D DQ D ,DQP D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ C , DQP C DQ C , DQP C BYTE BW C BYTE OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQ B , DQP B E DQ B , DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQ
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Pin Configurations 100-pin TQFP Pinout (3 Chip Enable) DQP DQPB C 1 80 NC 1 80 A DQC 2 79 DQB NC NC 2 79 DQc 3 78 DQB NC NC 3 78 V DDQ 4 77 V DDQ V DDQ V 4 77 DDQ V SSQ 5 76 V SSQ V SSQ V 5 76 SSQ DQC 6 75 DQB NC NC 6 75 DQC DQB 7 74 NC DQPA 7 74 DQC DQB 8 73 DQB 8 73 DQA DQC DQB 9 72 DQB 9 72 DQA V V SSQ 10 71 V SSQ SSQ 10 71 V SSQ V DDQ 11 70 V DDQ V DDQ 11 70 V DDQ DQC 12 69 DQB DQB DQA 12 69 DQC 13 68 DQB DQB DQA 13 68 NC 14 67 V SS NC
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Pin Configurations (continued) 119-Ball BGA Pinout CY7C1380FV25 (512K x 36) 1 23 4 5 6 7 A V AA A A V ADSP DDQ DDQ B NC/288M AA ADSC A A NC/576M C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V CE V DQ DQ C C SS 1 SS B B F V DQ V V DQ V OE DDQ C SS SS B DDQ G DQ DQ BW BW DQ DQ ADV C C C B B B H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW D
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1380DV25 (512K x 36) 1 234 5 6 7 89 10 11 A NC/288M A NC A CE BW BW CE BWE ADSC ADV 1 C B 3 B NC/144M A CE2 BW BW CLK GW OE ADSP A NC/576M D A DQP NC V V V V V V V NC/1G DQP C C DDQ SS SS SS DDQ B SS SS D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C DD SS DD B C DDQ SS
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Pin Definitions Name IO Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the rising 0 1 [2] Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled 1 2 3 active. A1: A0 are fed to the two-bit counter. Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to BW , BW A B Synchronous the SRAM. Sampled on the rising edge of C
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Pin Definitions (continued) Name IO Description V IO Ground Ground for the IO circuitry. SSQ V IO Power Supply Power supply for the IO circuitry. DDQ MODE Input- Selects burst order. When tied to GND selects linear burst sequence. When tied to Static V or left floating selects interleaved burst sequence. This is a strap pin and must DD remain static during device operation. Mode pin has an internal pull up. TDO JTAG serial output Serial d
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 ADSP triggered write accesses require two clock cycles to Burst Sequences complete. If GW is asserted LOW on the second clock rise, the The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ data presented to the DQs inputs is written into the CY7C1382FV25 provides a two-bit wraparound counter, fed corresponding address location in the memory array. If GW is by A1: A0, that implements either an interleaved or linear burst HIGH, then the write operation
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 [4, 5, 6, 7, 8] Truth Table Operation Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State Sleep Mode, Power Down None
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 [6, 9] Truth Table for Read/Write Function (CY7C1380DV25/CY7C1380FV25) GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – (DQ and DQP) H L HHH L A A Write Byte B – (DQ and DQP)H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP) H LH LH H C C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQ and DQP) H L L HHH D D Write Bytes D, A H L L H H L Wr
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 registers. The register between TDI and TDO is chosen by the IEEE 1149.1 Serial Boundary Scan (JTAG) instruction that is loaded into the TAP instruction register. For The CY7C1380DV25/CY7C1382DV25 incorporates a serial information on loading the instruction register, see TAP boundary scan test access port (TAP). This part is fully Controller State Diagram. TDI is internally pulled up and can compliant with 1149.1. The TAP operates using be un
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Bypass Register The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test To save time when serially shifting data through registers, it is logic reset state. sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the SAMPLE Z TDI and TDO balls. This allows data to be shifted through the The SAMPLE Z instruction cau
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 instruction. When HIGH, it will enable the output buffers to directly control the output Q-bus pins. Note that this bit is drive the output bus. When LOW, this bit will place the output preset HIGH to enable the output when the device is powered bus into a High-Z condition. up, and also when the TAP controller is in the Test-Logic-Reset state. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent Input pulse levels .................................................V to 2.5V 1.25V SS Input rise and fall time..................................................... 1 ns 50Ω Input timing reference levels.........................................1.25V TDO Output reference levels.................................................1.25V Z = 50Ω O 20pF Test load termination supply volta
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 [13, 15] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N7 32 C11 62 D2 3 N10 33 A11 63 E2 4P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 8
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage........................................... >2001V the device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C La
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 [18] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit C Input Capacitance T = 25°C, f = 1 MHz, 5 8 9 pF IN A V /V = 2.5V DD DDQ C Clock Input Capacitance 5 8 9 pF CLK C Input/Output Capacitance 5 8 9 pF IO [18] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 28.66 23.8
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Switching Characteristics [19, 20] Over the Operating Range 250 MHz 200 MHz 167 MHz Parameter Description Min. Max Min. Max. Min. Max Unit [21] t V (Typical) to the First Access 1 11 ms POWER DD Clock t Clock Cycle Time 4.0 56 ns CYC t Clock HIGH 1.7 2.0 2.2 ns CH t Clock LOW 1.7 2.0 2.2 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.0 3.4 ns CO t Data Output Hold After CLK Rise 1.0 1.3 1.3 ns DOH [22, 23, 24] t Clock to Low-Z 1
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CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 Switching Waveforms [25] Read Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE, BWx Deselect t t CES CEH cycle CE t t ADVS ADVH ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Data Out (Q) High-Z t CO Burst wraps around to its initial state Single READ BURST REA
