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CY7C1471V33
CY7C1473V33
CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
[1]
Features Functional Description
• No Bus Latency™ (NoBL™) architecture eliminates dead The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
cycles between write and read cycles 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst
SRAMs designed specifically to support unlimited true
• Supports up to 133 MHz bus operations with zero wait states
back-to-back read or write operat
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram – CY7C1471V33 (2M x 36) ADDRESS A0, A1, A A1 REGISTER A1' D1 Q1 A0 A0' D0 Q0 MODE BURST CE ADV/LD LOGIC CLK C C CEN WRITE ADDRESS REGISTER O U T P D S A U E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BW B AND DATA COHERENCY T DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1473V33 (4M x 18
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram – CY7C1475V33 (1M x 72) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U A ADV/LD T N T T S BW a A R MEMORY E B WRITE E DQ s BW b ARRAY S U G DRIVERS BW c A T F DQ Pa WRITE REGISTRY I M F E AND DATA COHERENCY BW d S DQ Pb P E E CONTROL LOGIC T S R R BW e DQ Pc E S I R DQ Pd BW f N S G BW g DQ Pe E E BW h DQ Pf DQ Pg DQ Ph WE
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations 100-Pin TQFP Pinout DQP 80 1 C DQP B DQ 79 2 DQ C B DQ 78 3 C DQ B V 77 4 V DDQ DDQ V 76 5 SS V SS DQ 75 C 6 DQ B BYTE C BYTE B DQ 74 7 C DQ B DQ 73 8 DQ C B DQ 72 9 C DQ B V 71 10 V SS SS V 70 11 DDQ V DDQ DQ 69 C 12 DQ B DQ 68 13 C DQ B CY7C1471V33 NC 67 14 V SS V 66 15 NC DD NC 65 16 V DD V 64 ZZ 17 SS DQ 63 D 18 DQ A DQ 62 19 DQ D A V 61 20 DDQ V DDQ V 60 21 V SS SS DQ 59 22 D DQ A DQ 58 23 DQ BYTE D D A BYTE A DQ 57 24 D DQ A DQ 56 D
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 100-Pin TQFP Pinout NC 80 1 A NC 79 2 NC NC 78 3 NC V 77 4 DDQ V DDQ V 76 SS 5 V SS NC 75 6 NC NC 74 7 DQP A DQ 73 8 B DQ A DQ 72 B 9 DQ A V 71 10 SS V SS V 70 DDQ 11 V DDQ DQ 69 12 DQ B A DQ 68 B 13 DQ A CY7C1473V33 NC 67 14 V SS BYTE A V 66 DD 15 NC BYTE B NC 65 16 V DD V 64 17 ZZ SS DQ 63 18 DQ B A DQ 62 19 B DQ A V 61 20 V DDQ DDQ V 60 21 SS V SS DQ 59 22 DQ B A DQ 58 23 B DQ A DQP 57 24 NC B NC 56 25 NC V 55 26 V SS SS V
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V33 (2M x 36) 1 23 4 5 6 7 89 10 11 NC/576M CE BW BW CE CEN ADV/LD A A NC A A 1 C B 3 NC/1G A CE2 BW BW CLK WE OE A A NC B D A C DQP NC V V V V V V V NC DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V DQ DQ D V V V C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V DQ DQ E V V V C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ V V V V V V V
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1475V33 (1M × 72) 1 2 3 4 567 8 9 10 11 A DQg DQgAA CE ADV/LDA CEA DQb DQb 2 3 B DQg DQg BWS BWS NC WE A BWS BWS DQb DQb c g b f C DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb h d 1 e a D DQg NC DQg V NC/1G OE NC V SS NC DQb SS DQb E DQPg DQPc V V V V V V V DDQ DDQ DD DD DD DDQ DDQ DQPf DQPb F DQc DQc V V V NC V V V DQf SS SS SS SS SS DQf SS G DQc V DQc V V V NC DD V V DDQ DDQ DQf D
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Definitions Name IO Description A , A , A Input- Address Inputs used to select one of the address locations. Sampled at the rising edge 0 1 Synchronous of the CLK. A are fed to the two-bit burst counter. [1:0] BW , BW , Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. A B BW , BW , Synchronous Sampled on the rising edge of CLK. C D BW , BW , E F BW , BW G H WE Input- Write Enable Input, Active LOW. Sampled on the r
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Definitions (continued) Name IO Description TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the output JTAG feature is not used, this pin must be left unconnected. This pin is not available on Synchronous TQFP packages. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not used, this pin can be left floating or connected to V
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CY7C1471V33 CY7C1473V33 CY7C1475V33 The data written during the write operation is controlled by Interleaved Burst Address Table BW signals. The CY7C1471V33, CY7C1473V33, and X (MODE = Floating or V ) DD CY7C1475V33 provides Byte Write capability that is described in the “Truth Table for Read/Write” on page 12. The input WE First Second Third Fourth Address Address Address Address with the selected BW input selectively writes to only the X A1: A0 A1: A0 A1: A0 A1: A0 desired bytes. Bytes not se
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Truth Table [2, 3, 4, 5, 6, 7, 8] The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows. Address Operation CE CE ZZ ADV/LD WE BW OE CEN CLK DQ CE 1 2 X 3 Used Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Continue Deselect Cycle None X X X L H X X X L L->H Tri-State Read Cycle External L H L L L H X L L L->H Data Out (Q) (Begin Burst)
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Truth Table for Read/Write [2, 3, 9] The read-write truth table for CY7C1471V33 follows. Function WE BW BW BW BW A B C D Read H X X X X Write No bytes written L HHHH Write Byte A – (DQ and DQP) L L HHH A A Write Byte B – (DQ and DQP)LHLHH B B Write Byte C – (DQ and DQP)LHHLH C C Write Byte D – (DQ and DQP) L HHH L D D Write All Bytes L L L L L Truth Table for Read/Write [2, 3, 9] The read-write truth table for CY7C1473V33 follows. Function WE BW BW b a Read H
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Test Access Port (TAP) IEEE 1149.1 Serial Boundary Scan (JTAG) Test Clock (TCK) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). The test clock is used only with the TAP controller. All inputs This port operates in accordance with IEEE Standard are captured on the rising edge of TCK. All outputs are driven 1149.1-1990 but does not have the set of functions required from the falling edge of TCK. for full 1
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CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 Registers are connected between the TDI and TDO balls and instructions are not fully implemented. enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through The TAP controller cannot be used to load address data or the instruction register. Data is serially loaded int
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CY7C1471V33 CY7C1473V33 CY7C1475V33 signal while in transition (metastable state). This does not Note that since the PRELOAD part of the command is not harm the device, but there is no guarantee as to the value that implemented, putting the TAP to the Update-DR state while is captured. Repeatable results may not be possible. performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. To guarantee that the boundary scan register captures the correct value of a signal, the
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CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP AC Switching Characteristics [10, 11] Over the Operating Range Parameter Description Min Max Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 5 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Ti
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CY7C1471V33 CY7C1473V33 CY7C1475V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Inpu
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Identification Register Definitions CY7C1471V33 CY7C1473V33 CY7C1475V33 Instruction Field Description (2Mx36) (4Mx18) (1Mx72) Revision Number (31:29) 000 000 000 Describes the version number [13] Device Depth (28:24) 01011 01011 01011 Reserved for internal use Architecture/Memory 001001 001001 001001 Defines memory type and architecture Type(23:18) Bus Width/Density(17:12) 100100 010100 110100 Defines width and density Cypress JEDEC ID Code (11:1) 00000110100
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4D2 24 P6 44 H11 64 B5 5E2 25 R6 45 G11 65 A5 6F1 26 R8 46 F11 66 A4 7G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2A2 30 T2 58 T11 86 B10 3B1 31 U1 59 T10 87 A11 4B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J1
