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CY7C1338G
4-Mbit (128K x 32) Flow-Through Sync SRAM
[1]
Features Functional Description
• 128K x 32 common I/O The CY7C1338G is a 128K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
• 3.3V core power supply (V )
DD
minimum glue logic. Maximum access delay from clock rise is
• 2.5V or 3.3V I/O supply (V )
DDQ 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
• Fast clock-to-output tim
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CY7C1338G Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum Standby Current 40 40 mA Pin Configurations 100-Pin TQFP Pinout NC 1 80 NC DQ 2 C 79 DQ B DQ 3 DQ C 78 B V 4 V DDQ 77 DDQ V 5 V SSQ 76 SSQ DQ 6 C 75 DQ B DQ 7 C 74 DQ B DQ 8 BYTE C C 73 DQ BYTE B B DQ 9 C 72 DQ B V 10 SSQ 71 V SSQ V 11 DDQ 70 V DDQ DQ 12 C 69 DQ B DQ 13 C 68 DQ B NC 14 67 V SS V 15 NC DD 66 CY7C1338G NC 16 65 V DD V 17 ZZ SS 64 DQ 18 DQ D 63 A DQ 19 62 DQ D
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CY7C1338G Pin Configurations (continued) 119-Ball BGA Pinout 1 2 34 5 6 7 A V AA A AA V ADSP DDQ DDQ B NC/288M CE A A NC/576M ADSC NC/9M 2 C NC/144M A A V A A NC/1G DD D DQ NC V NC V NC DQ C SS SS B E DQ DQ V V DQ DQ CE C C SS SS B B 1 V DQ V V DQ V F OE DDQ C SS SS B DDQ G DQ DQ BW BW DQ DQ ADV C C B B C B H DQ DQ V V DQ DQ C C SS GW SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D D A A A M V DQ V V DQ V BWE DDQ D SS SS A DDQ N DQ DQ V A1
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CY7C1338G Pin Definitions (continued) Name I/O Description ADSP Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A are [1:0] also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. ASDP is ignored when CE is deasserted HIGH 1 ADSC Input- Address Strobe from Controller, sampled on the rising edge of CLK, active
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CY7C1338G Single Write Accesses Initiated by ADSP A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. This access is initiated when the following conditions are A LOW on MODE will select a linear burst sequence. A HIGH satisfied at clock rise: (1) CE , CE , CE are all asserted 1 2 3 on MODE will select an interleaved burst order. Leaving active, and (2) ADSP is asserted LOW. The addresses MODE unconnected will cause the
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CY7C1338G [2, 3, 4, 5, 6] Truth Table Address Cycle Description Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselected Cycle, Power-down None H X X L X L X X X L-H Tri-State Deselected Cycle, Power-down None L L X L L X X X X L-H Tri-State Deselected Cycle, Power-down None L X H L L X X X X L-H Tri-State Deselected Cycle, Power-down None L L X L H L X X X L-H Tri-State Deselected Cycle, Power-down None X X X L H L X X X L-H Tri-State Sleep Mode, Power-down None X X X H X X X X X X Tri-
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CY7C1338G [2, 7] Partial Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A H L HHH L Write Byte B H L H H L H Write Bytes B, A H L H H L L Write Byte C H LH LH H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D H L L HHH Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, B H L L L H H Write Bytes D, B, A H L L L H L Write Bytes D, C, A
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CY7C1338G DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.....................................................
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CY7C1338G [10] Capacitance 119 BGA 100 TQFP Parameter Description Test Conditions Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 55 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 5 pF CLK V = 3.3V DDQ C Input/Output Capacitance 5 7 pF I/O [10] Thermal Resistance 100 TQFP 119 BGA Parameter Description Test Conditions Package Package Unit ΘJA Thermal Resistance Test conditions follow standard test 30.32 34.1 °C/W (Junction to Ambient) methods and procedures for measuring thermal impe
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CY7C1338G [11, 12, 13, 14, 15, 16] Switching Characteristics Over the Operating Range –133 –100 Parameter Description Min. Max. Min. Max. Unit [11] t V (Typical) to the first Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 2.5 4.0 ns CH t Clock LOW 2.5 4.0 ns CL Output Times t Data Output Valid After CLK Rise 6.5 8.0 ns CDV t Data Output Hold After CLK Rise 2.0 2.0 ns DOH [12, 13, 14] t Clock to Low-Z 00 ns CLZ [12, 13, 14] t Clock to High-Z 3.5 3.5 ns CHZ t OE LOW to
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CY7C1338G Timing Diagrams [17] Read Cycle Timing t CYC CLK t t CH CL t t ADH ADS ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 t t WES WEH GW, BWE,BW [A:D] Deselect Cycle t t CES CEH CE t t ADVH ADVS ADV ADV suspends burst. OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Data Out (Q) High-Z t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On this diagram, when CE is LOW: CE is L
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CY7C1338G Timing Diagrams (continued) [17, 18] Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADS ADH t t ADS ADH ADSC t t AS AH A1 A2 A3 ADDRESS Byte write signals are ignored for first cycle when ADSP initiates burst t t WES WEH BWE, BW[A:D] t t WES WEH GW t t CEH CES CE t t ADVS ADVH ADV ADV suspends burst OE t t DH DS Data in (D) High-Z D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) t OEHZ Data Out (Q) BURST READ BURST WRITE
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CY7C1338G Timing Diagrams (continued) [17, 19, 20] Read/Write Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CES CEH CE ADV OE t t DS DH t OELZ High-Z D(A3) D(A5) D(A6) Data In (D) t OEHZ t CDV Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is
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CY7C1338G Timing Diagrams (continued) [21, 22] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05521 Rev. *D Page 14 of 17
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CY7C1338G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Part and Package Type Range 133 CY7C1338G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1338G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1338G-133BGXC 119-ball Ball Grid Array (14 x 22
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CY7C1338G Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25MCAB A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 16 237 4 5 7 65 43 21 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U 1.27 0.70 REF. A 3.81 12.00 7.62 B 14.00±0.20 0.15(4X) 30° TYP. 51-85115-*B SEATING PLANE C Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of th
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CY7C1338G Document History Page Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM Document Number: 38-05521 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 224369 See ECN RKF New data sheet *A 278513 See ECN VBL Deleted 66 MHz Changed TQFP to PB-Free TQFP in Ordering Info section Added PB-Free BG package *B 333626 See ECN SYT Removed 117-MHz speed bin Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Packages as per JEDEC standards and
