Instruction d'utilisation Cypress CY7C1018CV33

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CY7C1018CV33
128K x 8 Static RAM
device has an automatic power-down feature that significantly
Features
reduces power consumption when deselected.
• Pin- and function-compatible with CY7C1018BV33
Writing to the device is accomplished by taking Chip Enable
•High speed
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O through I/O ) is then written into the location
—t = 10 ns
0 7
AA
specified on the address pins (A through A ).
0 16
• CMOS for optimum speed/power
Reading f

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CY7C1018CV33 Selection Guide -10 -12 -15 Unit Maximum Access Time 10 12 15 ns Maximum Operating Current Comm’l 90 85 80 mA Ind’l 85 mA Maximum Standby Current 5 5 5 mA Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage........................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current...................................

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CY7C1018CV33 [4] AC Test Loads and Waveforms ALL INPUT PULSES R 317Ω 3.0V 3.3V 90% 90% OUTPUT 10% 10% GND R2 30 pF 351Ω Fall Time: 1 V/ns Rise Time: 1 V/ns (a) (b) High-Z characteristics: R 317Ω 3.3V OUTPUT R2 5 pF 351Ω (c) [5] Switching Characteristics Over the Operating Range -10 -12 -15 Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 10 12 15 ns RC t Address to Data Valid 10 12 15 ns AA t Data Hold from Address Change 3 3 3 ns OHA t CE LOW to Data Va

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CY7C1018CV33 Switching Waveforms [11, 12] Read Cycle No. 1 t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [12, 13] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PD t ICC PU V CC 50% 50% SUPPLY ISB CURRENT [14, 15] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t SCE t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID Notes: 11. Device is continuously selected. OE, C

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CY7C1018CV33 Switching Waveforms (continued) [14, 15] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t t SD HD DATA I/O DATA VALID IN NOTE 16 t HZOE [10, 15] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 16 DATA I/O DATA VALID t t LZWE HZWE Truth Table CE OE WE I/O –I/O Mode Power 0 7 H X X High-Z Power-down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write A

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CY7C1018CV33 Ordering Information Speed Package Operating (ns) Ordering Code Diagram Package Type Range 10 CY7C1018CV33-10VC 51-85041 32-lead 300-mil Molded SOJ Commercial 12 CY7C1018CV33-12VC 32-lead 300-mil Molded SOJ Commercial CY7C1018CV33-12VXI 32-lead 300-mil Molded SOJ (Pb-Free) Industrial 15 CY7C1018CV33-15VXC 32-lead 300-mil Molded SOJ (Pb-Free) Commercial Package Diagram 32-lead (300-mil) Molded SOJ (51-85041) 51-85041-*A All product and company names mentioned in this document are

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CY7C1018CV33 Document History Page Document Title: CY7C1018CV33 128K x 8 Static RAM Document Number: 38-05131 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 109426 12/14/01 HGK New Data Sheet *A 113432 04/10/02 NSL AC Test Loads split based on speed *B 115046 05/30/02 HGK I and I modified CC SB1 *C 116476 09/16/02 CEA Add applications foot note on data sheet, pg 1 *D 493543 See ECN NXR Added Industrial Operating Range Removed 8 ns speed bin from Product offering Changed the