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CY7C1218H
1-Mbit (32K x36) Pipelined Sync SRAM
[1]
Features Functional Description
• Registered inputs and outputs for pipelined operation The CY7C1218H SRAM integrates 32K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• 32K × 36 common I/O architecture
counter for internal burst operation. All synchronous inputs are
• 3.3V core power supply (V )
DD gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
• 2
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CY7C1218H Selection Guide 166 MHz 133 MHz Unit Maximum Access Time 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100-Pin TQFP Top View DQP C 1 80 DQP B DQ C DQ 2 79 B DQ C 3 78 DQ B V DDQ 4 77 V DDQ V SSQ V 5 76 SSQ DQ C 6 75 DQ B DQ BYTE C BYTE B C 7 74 DQ B DQ DQ C 8 73 B DQ C 9 72 DQ B V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ DQ C 12 69 DQ B DQ C DQ 13 68 B NC 14 67 V SS V DD 15 66 NC NC V 16 65 CY7C1218H DD V SS 17 64 ZZ DQ D 18 63 DQ A DQ
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CY7C1218H Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the 32K address locations. Sampled at the rising edge 0 1 Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A 1 2 3 1 0 feed the 2-bit counter. BW , BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. A B Synchronous Sampled on the rising edge of CLK. BW , BW C D GW Input- Global Write Enable
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CY7C1218H signals. The CY7C1218H provides Byte Write capability that Functional Overview is described in the Write Cycle Descriptions table. Asserting All synchronous inputs pass through input registers controlled the Byte Write Enable input (BWE) with the selected Byte by the rising edge of the clock. All data outputs pass through Write (BW ) input, will selectively write to only the desired [A:D] output registers controlled by the rising edge of the clock. bytes. Bytes not selected during a By
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CY7C1218H Linear Burst Address Table (MODE = GND) Interleaved Burst Address Table (MODE = Floating or V ) DD First Second Third Fourth Address Address Address Address First Second Third Fourth A , A A , A A , A A , A 1 0 1 0 1 0 1 0 Address Address Address Address A , A A , A A , A A , A 00 01 10 11 1 0 1 0 1 0 1 0 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep
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CY7C1218H [2, 3, 4, 5, 6, 7] Truth Table (continued) Next Cycle Add. Used ZZ CE CE CE ADSP ADSC ADV OE DQ Write 1 2 3 Continue Write Next L X X X H H H X Tri-State Write Continue Write Next L H X X X H H X Tri-State Write Suspend Write Current L X X X H H H X Tri-State Write Suspend Write Current L H X X X H H X Tri-State Write ZZ “Sleep” None H X X X XXXX Tri-State X [2, 3] Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – (DQ and DQP) H L
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CY7C1218H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch-up Current.....................................................
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CY7C1218H [10] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V. DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [10] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods 30.32 °C/W JA (Junction to Ambient) and procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resist
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CY7C1218H [11, 12] Switching Characteristics Over the Operating Range 166 MHz 133 MHz Parameter Description Min. Max. Min. Max. Unit [13] t V (Typical) to the First Access 1 1 ms POWER DD Clock t Clock Cycle Time 6.0 7.5 ns CYC t Clock HIGH 2.5 3.0 ns CH t Clock LOW 2.5 3.0 ns CL Output Times t Data Output Valid after CLK Rise 3.5 4.0 ns CO t Data Output Hold after CLK Rise 1.5 1.5 ns DOH [14, 15, 16] t Clock to Low-Z 0 0 ns CLZ [14, 15, 16] t Clock to High-Z 3.5 4.0 ns CHZ t OE LOW to Output Va
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CY7C1218H Switching Waveforms [17] Read Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH A1 A2 A3 ADDRESS Burst continued with t t WES WEH new base address GW, BWE, BW[A:D] Deselect t t CES CEH cycle CE t t ADVS ADVH ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Data Out (Q) High-Z Q(A1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On t
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CY7C1218H Switching Waveforms (continued) [17, 18] Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADH ADS t t ADS ADH ADSC t t AH AS A1 A2 A3 ADDRESS Byte write signals are ignored for first cycle when t t ADSP initiates burst WES WEH BWE, BW[A :D] t t WES WEH GW t t CES CEH CE t t ADVH ADVS ADV ADV suspends burst OE t t DS DH Data In (D) D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z t OEHZ Data Out (Q) BURST READ Single W
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CY7C1218H Switching Waveforms (continued) [17, 19, 20] Read/Write Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CES CEH CE ADV OE t t t CO DS DH t OELZ Data In (D) High-Z D(A3) D(A5) D(A6) t t OEHZ CLZ Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) High-Z Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unles
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CY7C1218H Switching Waveforms (continued) [21, 22] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05667 Rev. *B Page 13 of 16 [+] Feedback
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CY7C1218H Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 100 CY7C1218H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1218H-100AXI Industrial 133 CY7C1218H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1
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CY7C1218H Package Diagram 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. 0°-7° BODY LENGTH DIMENSIONS ARE MAX
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CY7C1218H Document History Page Document Title: CY7C1218H 1-Mbit (32K x36) Pipelined Sync SRAM Document Number: 38-05667 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 343896 See ECN PCI New Data Sheet *A 430678 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added 2.5VI/O option Changed Three-State to Tri-State Included Maximum Ratings for V relative to GND DDQ Modified “Input Load” to “Input
