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CY7C1324H
2-Mbit (128K x 18) Flow-Through Sync SRAM
first address in a burst and increments the address automati-
Features
cally for the rest of the burst access. All synchronous inputs
• 128K x 18 common I/O are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
• 3.3V core power supply
addresses, all data inputs, address-pipelining Chip Enable
• 3.3V/2.5V I/O supply
(CE ), depth-expansion Chip Enables (CE and CE ), Burst
1 2 3
C
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CY7C1324H Selection Guide 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 225 mA Maximum Standby Current 40 mA Pin Configurations 100-pin TQFP Pinout NC 1 80 A NC 2 79 NC NC 3 NC 78 V 4 V DDQ 77 DDQ V 5 V SS 76 SS NC 6 75 NC NC 7 74 DQP B DQ B 8 73 DQ A DQ B 9 72 DQ A V 10 SS 71 V SS V 11 DDQ 70 V DDQ DQ 12 B 69 DQ A DQ 13 B 68 DQ A NC 14 67 V SS V 15 NC DD 66 CY7C1324H NC 16 BYTE A 65 V DD BYTE B V ZZ 17 SS 64 DQ 18 DQ B 63 A DQ 19 DQ B 62 A V 20 61 V DDQ DDQ V SS 21 60 V
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CY7C1324H Pin Definitions Name I/O Description A0, A1, A Input- Address Inputs used to select one of the 128K address locations. Sampled at the rising Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. 1 2 3 A feed the 2-bit counter. [1:0] BW BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the A, B Synchronous SRAM. Sampled on the rising edge of CLK. GW Input- Global Write Enable Input, active LO
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CY7C1324H active, (2) ADSC is asserted LOW, (3) ADSP is deasserted Functional Overview HIGH, and (4) the write input signals (GW, BWE, and BW[A:B]) All synchronous inputs pass through input registers controlled indicate a write access. ADSC is ignored if ADSP is active by the rising edge of the clock. Maximum access delay from LOW. the clock rise (t ) is 6.5 ns (133-MHz device). CDV The addresses presented are loaded into the address register The CY7C1324H supports secondary cache in systems
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CY7C1324H ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V 40 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ Active to sleep current This parameter is sampled 2t ns ZZI CYC t ZZ Inactive to exit sleep current This parameter is sampled 0 ns RZZI [2, 3, 4, 5] Truth Table ADDRESS Cycle Description Used CE CE CE ZZ ADSP ADSC ADV WE OE CLK DQ 1 2 3
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CY7C1324H [2, 3] Truth Table for Read/Write Function GW BWE BW BW B A Read H H X X Read H L H H Write Byte (A, DQP)HLHL A Write Byte (B, DQP)HLLH B Write All Bytes H L L L Write All Bytes L X X X Document #: 001-00208 Rev. *B Page 6 of 15 [+] Feedback
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CY7C1324H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current...................................................
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CY7C1324H [8] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V. DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [8] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods and proce- 30.32 °C/W JA (Junction to Ambient) dures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resi
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CY7C1324H [9, 10] Switching Characteristics Over the Operating Range -133 Parameter Description Min. Max. Unit [11] t V (Typical) to the First Access 1ms POWER DD Clock t Clock Cycle Time 7.5 ns CYC t Clock HIGH 2.5 ns CH t Clock LOW 2.5 ns CL Output Times t Data Output Valid after CLK Rise 6.5 ns CDV t Data Output Hold after CLK Rise 2.0 ns DOH [12, 13, 14] t Clock to Low-Z 0ns CLZ [12, 13, 14] t Clock to High-Z 3.5 ns CHZ OE LOW to Output Valid t 3.5 ns OEV [12, 13, 14] OE LOW to Output L
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CY7C1324H Timing Diagrams [15] Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 t t WES WEH GW, BWE,BW [A:B] Deselect Cycle t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst. OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Data Out (Q) Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) High-Z t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 15. On this diagram, when CE is LOW, CE
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CY7C1324H Timing Diagrams (continued) [15, 16] Write Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC extends burst. t t ADS ADH t t ADS ADH ADSC t t AS AH A1 A2 A3 ADDRESS Byte write signals are ignored for first cycle when ADSP initiates burst. t t WES WEH BWE, BW[A:B] t t WEH WES GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst. OE t t DS DH Data in (D) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z D(A1) t OEHZ Data Out (Q) BURST READ Single
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CY7C1324H Timing Diagrams (continued) [15, 17, 18] Read/Write Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:B] t t CES CEH CE ADV OE t t DS DH t OELZ High-Z D(A3) D(A5) D(A6) Data In (D) t OEHZ t CDV Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or A
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CY7C1324H Timing Diagrams (continued) [19, 20] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode. Document #: 001-00208 Rev. *B Page 13 of 15 [+] Feedback
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CY7C1324H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 133 CY7C1324H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1324H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial Package Diagram 100-pin TQFP (14
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CY7C1324H Document History Page Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Through Sync SRAM Document Number: 001-00208 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NXR Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 100 MHz Speed-bin Changed Three-State to Tri-State. Modified “Input Load” to “Input
