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CY7C1231H
2-Mbit (128K x 18) Flow-Through SRAM
with NoBL™ Architecture
[1]
Features
Functional Description
• Can support up to 133-MHz bus operations with zero The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
wait states Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
— Data is transferred on every clock
insertion of wait states. The CY7C1231H is equipped with the
• Pin compatible and functionally equivalent to ZBT™
adv
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CY7C1231H Selection Guide 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 225 mA Maximum CMOS Standby Current 40 mA Pin Configuration 100-pin TQFP Pinout NC 80 1 A NC 79 2 NC NC 78 3 NC V 77 4 DDQ V DDQ V 76 SS 5 V SS NC 75 6 NC NC 74 7 DQP A DQ 73 8 DQ B A DQ 72 9 B DQ A V 71 10 V SS SS V 70 11 DDQ V DDQ DQ 69 12 DQ B A DQ 68 13 B DQ A CY7C1231H NC 67 14 V SS V 66 15 DD NC BYTE B NC 65 16 V DD V 64 ZZ BYTE A 17 SS DQ 63 18 DQ B A DQ 62 19 B DQ A V 61 20 V DDQ DDQ V 60 21
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CY7C1231H Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of 0 1 Synchronous the CLK. A are fed to the two-bit burst counter. [1:0] BW Input- Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the [A:B] Synchronous rising edge of CLK. WE Input- Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This Synchronous sign
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CY7C1231H Single Write Accesses Functional Overview Write accesses are initiated when the following conditions are The CY7C1231H is a synchronous flow-through burst SRAM satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE , 1 2 designed specifically to eliminate wait states during and CE are ALL asserted active, and (3) the Write signal WE 3 Write-Read transitions. All synchronous inputs pass through is asserted LOW. The address presented to the address bus input registers controlle
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CY7C1231H Interleaved Burst Sequence Linear Burst Address Table (MODE = GND) First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V − 0.2V 40 mA DDZZ DD t Device
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CY7C1231H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current...................................................
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CY7C1231H [11] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLOCK V = 2.5V DDQ C I/O Capacitance 5 pF I/O [11] Thermal Resistance 100 TQFP Parameters Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods and 30.32 °C/W JA (Junction to Ambient) procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resistance
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CY7C1231H [12, 13] Switching Characteristics Over the Operating Range -133 Parameter Description Min. Max. Unit [14] t V (Typical) to the first Access 1 ms POWER DD Clock t Clock Cycle Time 7.5 ns CYC t Clock HIGH 2.5 ns CH t Clock LOW 2.5 ns CL Output Times t Data Output Valid after CLK Rise 6.5 ns CDV t Data Output Hold after CLK Rise 2.0 ns DOH [15, 16, 17] t Clock to Low-Z 0 ns CLZ [15, 16, 17] t Clock to High-Z 3.5 ns CHZ OE LOW to Output Valid t 3.5 ns OEV [15, 16, 17] OE LOW to Output
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CY7C1231H Switching Waveforms [18, 19, 20] Read/Write Waveforms t 123 456789 10 CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BW[A:B] A1 A2 A3 A4 A5 A6 A7 ADDRESS t CDV t t AS AH t t t t DOH CLZ OEV CHZ D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) D(A7) DQ t OEHZ t t DS DH t DOH t OELZ OE COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: For this waveform ZZ
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CY7C1231H Switching Waveforms (continued) [18, 19, 21] NOP, STALL and Deselect Cycles 123 456 789 10 CLK CEN CE ADV/LD WE BW[A:B] ADDRESS A1 A2 A3 A4 A5 t CHZ DQ D(A1) Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED [22, 23] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 21. The IGNORE
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CY7C1231H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial Package Diagram 100-pin TQFP (14
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CY7C1231H Document History Page Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-00207 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NXR Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 100 MHz Speed-bin Changed Three-State to Tri-State. Modified “Inp
