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CY7C1303BV25
CY7C1306BV25
18-Mbit Burst of 2 Pipelined SRAM with
QDR™ Architecture
Features Functional Description
• Separate independent Read and Write data ports The CY7C1303BV25 and CY7C1306BV25 are 2.5V
Synchronous Pipelined SRAMs equipped with QDR™ archi-
— Supports concurrent transactions
tecture. QDR architecture consists of two separate ports to
• 167-MHz Clock for high bandwidth
access the memory array. The Read port has dedicated Data
— 2.5 ns Clock-to-Valid access time
Outputs to su
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CY7C1303BV25 CY7C1306BV25 Logic Block Diagram (CY7C1303BV25) D [17:0] 18 Write Write Data Reg Data Reg Address A Register (18:0) Address A (18:0) 19 Register 19 512Kx18 512Kx18 Memory Memory Array Array K CLK RPS Control K Gen. Logic C Read Data Reg. C 36 18 Vref 18 Reg. Reg. 18 Control WPS Logic 18 BWS 0 Reg. Q BWS [17:0] 1 18 Logic Block Diagram (CY7C1306BV25) D [35:0] 36 Write Write Data Reg Data Reg Address A Register (17:0) Address A (17:0) 18 Register 18 256Kx36 256Kx36 Memory Memory Arr
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CY7C1303BV25 CY7C1306BV25 Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1303BV25 (1M x 18) 1 2 3456 7 8 9 10 11 A NC Gnd/ 144M NC/ 36M WPS BWS K NC RPS A Gnd/ 72M NC 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD V
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CY7C1303BV25 CY7C1306BV25 Pin Definitions Name I/O Description D Input- Data input signals, sampled on the rising edge of K and K clocks during valid write opera- [x:0] Synchronous tions. CY7C1303BV25 – D [17:0] CY7C1306BV25 – D [35:0] WPS Input- Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D to be ignored. [x:0] BWS
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CY7C1303BV25 CY7C1306BV25 Pin Definitions (continued) Name I/O Description NC/36M N/A Address expansion for 36M. This pin is not connected to the die and so can be tied to any voltage level on CY7C1303BV25/CY7C1306BV25. GND/72M Input Address expansion for 72M. This pin has to be tied to GND on CY7C1303BV25. NC/72M N/A Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306BV25. GND/144M Input Address expansion for 144M. This pin has to be tied to GND on CY7C1303BV25
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CY7C1303BV25 CY7C1306BV25 operation is identical to the operation if the device had zero Depth Expansion skew between the K/K and C/C clocks. All timing parameters The CY7C1303BV25 has a Port Select input for each port. remain the same in this mode. To use this mode of operation, This allows for easy depth expansion. Both Port Selects are the user must tie C and C HIGH at power-up.This function is sampled on the rising edge of the Positive Input Clock only (K). a strap option and not alterable
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CY7C1303BV25 CY7C1306BV25 [2, 8] Write Descriptions (CY7C1303BV25) BWS BWS KK Comments 0 1 L L L-H - During the Data portion of a Write sequence, both bytes (D ) are written into the device. [17:0] L L - L-H During the Data portion of a Write sequence, both bytes (D ) are written into the device. [17:0] L H L-H - During the Data portion of a Write sequence, only the lower byte (D ) is written into the [8:0] device. D remains unaltered. [17:9] L H - L-H During the Data portion of a Write seque
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CY7C1303BV25 CY7C1306BV25 TDI and TDO pins as shown in TAP Controller Block Diagram. IEEE 1149.1 Serial Boundary Scan (JTAG) Upon power-up, the instruction register is loaded with the These SRAMs incorporate a serial boundary scan test access IDCODE instruction. It is also loaded with the IDCODE port (TAP) in the FBGA package. This part is fully compliant instruction if the controller is placed in a reset state as with IEEE Standard #1149.1-1900. The TAP operates using described in the previou
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CY7C1303BV25 CY7C1306BV25 is loaded into the instruction register upon power-up or BYPASS whenever the TAP controller is given a test logic reset state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass SAMPLE Z register is placed between the TDI and TDO pins. The The SAMPLE Z instruction causes the boundary scan register advantage of the BYPASS instruction is that it shortens the to be connected between the TDI and TDO pins
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CY7C1303BV25 CY7C1306BV25 [9] TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05627 Rev. *A Page 10 of 19 [+] Feedback
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CY7C1303BV25 CY7C1306BV25 TAP Controller Block Diagram 0 Bypass Register Selection Selection TDI 2 1 0 TDO Circuitry Circuitry Instruction Register 29 31 30 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS [10, 14, 17] TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = −2.0 mA 1.7 V OH1 OH V Output HIGH Voltage I = −100 µA2.1 V OH2 OH V Output LOW Voltage I =
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CY7C1303BV25 CY7C1306BV25 [11, 12] TAP AC Switching Characteristics Over the Operating Range (continued) Parameter Description Min. Max. Unit Output Times t TCK Clock LOW to TDO Valid 20 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX [12] TAP Timing and Test Conditions 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z = 50Ω 0 1.25V C = 20 pF L 0V (a) GND t TL t TH Test Clock TCK t TCYC t TMSS t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t t TDOX TDOV Identification Regi
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CY7C1303BV25 CY7C1306BV25 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output driv
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CY7C1303BV25 CY7C1306BV25 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N
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CY7C1303BV25 CY7C1306BV25 [17] DC Input Voltage ............................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired.) Static Discharge Voltage.......................................... > 2001V Storage Temperature ................................–65°C to + 150°C (per MIL-STD-883, Method 3015) Ambient Temperature with Latch-up Current...........................................
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CY7C1303BV25 CY7C1306BV25 [23] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 2.5V. DD C Clock Input Capacitance 6 pF CLK V = 1.5V DDQ C Output Capacitance 7 pF O AC Test Loads and Waveforms V = 0.75V REF 0.75V V REF V REF 0.75V R = 50Ω OUTPUT [21] ALL INPUT PULSES Z = 50Ω 0 OUTPUT 1.25V Device R = 50Ω L 0.75V Under Device 0.25V Test 5pF Under V = 0.75V Slew Rate = 2 V/ns REF ZQ Test ZQ RQ = RQ = 250Ω 250Ω (a) (b) [21]
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CY7C1303BV25 CY7C1306BV25 [25, 26, 27] Switching Waveforms READ WRITE READ WRITE READ WRITE NOP WRITE NOP 12345 6 7 8 9 10 K t t t t KH KL CYC KHKH K RPS tSC tHC WPS A0 A1 A2 A3 A4 A5 A6 A t t t t SA HA SA HA D D10 D11 D30 D31 D50 D51 D60 D61 t t t SD HD t HD SD Q Q00 Q01 Q20 Q21 Q40 Q41 t CHZ t t t CLZ DOH DOH t t t t KHCH KHCH CO CO C t t t tCYC KH KL KHKH C DON’T CARE UNDEFINED Notes: 24. t , t , are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is m
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CY7C1303BV25 CY7C1306BV25 Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 167 CY7C1303BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1306BV25-167BZC CY7C1303BV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free C
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CY7C1303BV25 CY7C1306BV25 Document History Page Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Document Number: 38-05627 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 253010 See ECN SYT New Data Sheet *A 436864 See ECN NXR Converted from Preliminary to Final. Removed 133 MHz & 100 MHz from product offering. Included the Industrial Operating Range. Changed C/C Description in the Features Section & Pin Description Table. Ch
