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CY7C106D
CY7C1006D
1-Mbit (256K x 4) Static RAM
[1]
Features Functional Description
• Pin- and function-compatible with CY7C106B/CY7C1006B The CY7C106D and CY7C1006D are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
• High speed
Easy memory expansion is provided by an active LOW Chip
—t = 10 ns
AA
Enable (CE), an active LOW Output Enable (OE), and tri-state
• Low active power
drivers. These devices have an automatic power-down feature
that reduces power consumption b
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CY7C106D CY7C1006D [2] Pin Configuration SOJ Top View A V 1 28 0 CC A 1 2 27 A 17 A A 2 3 26 16 A 4 A 3 25 15 A 5 A 24 4 14 A 6 23 A 5 13 A 7 22 A 6 12 A 7 8 21 A 11 A 8 9 NC 20 A IO 9 10 19 3 A 10 11 18 IO 2 IO CE 12 17 1 13 16 IO OE 0 GND 14 15 WE Selection Guide CY7C106D-10 Unit CY7C1006D-10 Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Note 2. NC pins are not connected on the die. Document #: 38-05459 Rev. *E Page 2 of 11 [+] Feedback
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CY7C106D CY7C1006D [3] DC Input Voltage ............................... –0.5V to V + 0.5V Maximum Ratings CC Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage .......................................... > 2001V the device. These user guidelines are not tested. (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current ..............
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CY7C106D CY7C1006D [4] Capacitance Parameter Description Test Conditions Max Unit C : Addresses Input Capacitance T = 25°C, f = 1 MHz, V = 5.0V 7 pF IN A CC C : Controls 10 pF IN C Output Capacitance 10 pF OUT [4] Thermal Resistance 300-Mil 400-Mil Parameter Description Test Conditions Unit Wide SOJ Wide SOJ Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 59.16 58.76 °C/W JA (Junction to Ambient) four-layer printed circuit board Θ Thermal Resistance 40.84 40.54 °C/W JC (Junction t
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CY7C106D CY7C1006D [6] Switching Characteristics (Over the Operating Range) 7C106D-10 7C1006D-10 Parameter Description Unit Min Max Read Cycle [7] t V (typical) to the first access 100 µs power CC t Read Cycle Time 10 ns RC t Address to Data Valid 10 ns AA t Data Hold from Address Change 3 ns OHA t CE LOW to Data Valid 10 ns ACE t OE LOW to Data Valid 5 ns DOE t OE LOW to Low Z 0 ns LZOE [8, 9] t OE HIGH to High Z 5ns HZOE [9] t CE LOW to Low Z 3ns LZCE [8, 9] t CE HIGH to High Z 5ns HZCE [10]
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CY7C106D CY7C1006D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min Max Unit V V for Data Retention 2.0 V DR CC I Data Retention Current V = V = 2.0V, CE > V – 0.3V, 3mA CCDR CC DR CC V > V – 0.3V or V < 0.3V IN CC IN [4] t Chip Deselect to Data Retention Time 0 ns CDR [13, 14] t Operation Recovery Time t ns R RC Data Retention Waveform DATA RETENTION MODE 4.5V 4.5V V V > 2V DR CC t t CDR R CE Switching Waveforms [15, 16] Read Cycle No.1 (Address Tr
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CY7C106D CY7C1006D Switching Waveforms (continued) [18, 19] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t t SD HD DATA IO DATA VALID [18, 19] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t HD DATA IO DATA VALID t HZOE Notes 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. Data IO is high impedance if OE = V . IH Document #: 38-05459 Rev. *
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CY7C106D CY7C1006D Switching Waveforms (continued) [12, 19] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD DATA VALID DATA IO t t HZWE LZWE Truth Table CE OE WE Input/Output Mode Power H X X High Z Power-Down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write Active (I ) CC L H H High Z Selected, Outputs Disabled Active (I ) CC Ordering Information Speed Package Operating Package Type (ns) Ordering Code Diagram Range 10 CY7C
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CY7C106D CY7C1006D Package Diagrams Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. DETAIL A PIN 1 ID EXTERNAL LEAD DESIGN 14 1 0.291 0.330 0.300 0.350 0.026 0.032 0.013 15 28 0.019 0.014 0.020 OPTION 1 OPTION 2 0.697 SEATING PLANE 0.713 0.120 0.007 0.140 0.013 0.004 A 0.262 0.050 0.272 0.025 MI
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CY7C106D CY7C1006D Package Diagrams Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032 PIN 1 I.D 14 1 MIN. DIMENSIONS IN INCHES .435 MAX. .445 .395 .405 15 28 .720 .730 SEATING PLANE .128 .148 .007 .013 0.004 .026 .360 51-85032-*B .032 .025 MIN. .380 .015 .020 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05459 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject
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CY7C106D CY7C1006D Document History Page Document Title: CY7C106D/CY7C1006D, 1-Mbit (256K x 4) Static RAM Document Number: 38-05459 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 201560 See ECN SWI Advance information data sheet for C9 IPP *A 233693 See ECN RKF I ,I ,I Specs are modified as per EROS (Spec # 01-2165) CC SB1 SB2 Pb-free offering in the ‘ordering information’ *B 262950 See ECN RKF Added T Spec in Switching Characteristics table power Shaded ‘Ordering Information’
