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AMD Geode™ LX Processors
Data Book
February 2009
Publication ID: 33234H
AMD Geode™ LX Processors Data Book
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© 2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property
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Contents 33234H Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . .
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33234H Contents 6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.1 GeodeLink™ Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.2 GeodeLink™ Memory Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 6.3 Graphics Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 33234H List of Figures Figure 1-1. Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3-2. BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 4-1. GeodeLink™ Archite
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33234H List of Figures Figure 6-42. Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Figure 6-43. Message Passing Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Figure 6-44. Data Streaming Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Figure 6-45. BT.601 Mode Default Field Detection . .
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List of Tables 33234H List of Tables Table 2-1. Graphics Processor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3-1. Video Signal Definitions Per Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3-2. Buffer Type Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 3-3. Bootstrap Options . . . . . . . . . . .
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33234H List of Tables Table 6-11. Data Only Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table 6-12. Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 6-13. Pixel Ordering for 4-Bit Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 6-14. Example Vector Pattern . . . . . . . . .
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List of Tables 33234H Table 6-66. Panel Output Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Table 6-67. Register Settings for Dither Enable/Disable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Table 6-68. Display RGB Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Table 6-69. Standard GeodeLink™ Device MSRs Summary . . . . . . . .
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33234H List of Tables Table 8-12. sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 Table 8-13. ss Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Table 8-14. index Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Table 8-15. mod base Field Encoding . . . . . . . . . . . .
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Overview 33234H 1.0Overview 1 1.1 General Description AMD Geode™ LX processors are integrated x86 proces- While the processor core provides maximum compatibility sors specifically designed to power embedded devices for with the vast amount of Internet content available, the intel- entertainment, education, and business. Serving the needs ligent integration of several other functions, including of consumers and business professionals alike, it’s an graphics and video datapaths, offers a true syst
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33234H Overview ■ Power Management: 1.2 Features — LX 900@1.5W processor* (Unterminated): Total Dissipated Power (TDP) 5.1W, General Features 2.6W typical @ 600 MHz max power ■ Functional blocks include: — LX 800@0.9W processor* (Unterminated): —CPU Core Total Dissipated Power (TDP) 3.6W, — GeodeLink™ Control Processor 1.8W typical @ 500 MHz max power — GeodeLink Interface Units — LX 700@0.8W processor* (Unterminated): — GeodeLink Memory Controller Total Dissipated Power (TDP) 3.1W, — Grap
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Overview 33234H Display Controller GeodeLink™ PCI Bridge ■ Hardware frame buffer compression improves Unified ■ PCI 2.2 compliant Memory Architecture (UMA) memory efficiency ■ 3.3V signaling and 3.3V I/Os ■ CRT resolutions supported: ■ 33 to 66 MHz operation — Supports up to 1920x1440x32 bpp at 85 Hz — Supports up to 1600x1200x32 bpp at 100 Hz ■ 32-bit interface ■ Supports up to 1600x1200x32 bpp at 60 Hz for TFT ■ Supports virtual PCI headers for GeodeLink devices ■ Standard Definition (SD) reso
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33234H Overview 14 AMD Geode™ LX Processors Data Book
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Architecture Overview 33234H 2.0Architecture Overview 2 The CPU Core provides maximum compatibility with the 2.1.1 Integer Unit vast amount of Internet content available while the intelli- The Integer Unit consists of a single issue 8-stage pipeline gent integration of several other functions, including graph- and all the necessary support hardware to keep the pipe- ics, makes the AMD Geode™ LX processor a true system- line running efficiently. level multimedia solution. The instruction pipelin
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33234H Architecture Overview 2.1.2 Memory Management Unit integer core. The datapath is optimized for single precision arithmetic. Extended precision instructions are handled in The memory management unit (MMU) translates the linear microcode and require multiple passes through the pipe- address supplied by the integer unit into a physical address line. There is an execution pipeline and a load/store pipe- to be used by the cache unit and the internal bus interface line. This allows load/store o
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Architecture Overview 33234H � Hardware accelerated rotation BLTs 2.5 Graphics Processor The Graphics Processor is based on the graphics proces- � Color depth conversion sor used in the AMD Geode GX processor with several fea- � Paletized color tures added to enhance performance and functionality. Like its predecessor, the AMD Geode LX processor’s Graphics � Full 8x8 color pattern buffer Processor is a BitBLT/vector engine that supports pattern � Channel 3 - third DMA channel generation, source
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33234H Architecture Overview 2.7.2 TFT Controller 2.6 Display Controller The TFT Controller converts the digital RGB output of a The Display Controller performs the following functions: Video Mixer block to the digital output suitable for driving a 1) Retrieves graphics, video, and cursor data. TFT flat panel LCD. 2) Serializes the streams. The flat panel connects to the RGB port of the Video Mixer. It interfaces directly to industry standard 18-bit or 24-bit 3) Performs any necessary color look
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Architecture Overview 33234H set of interrupt registers. The AES module has two key 2.10 Security Block sources: one hidden 128-bit key stored in the “on-package” The AMD Geode LX processor has an on-chip AES 128-bit EEPROM, and a write only 128-bit key (reads as all zeros). crypto acceleration block capable of 44 Mbps throughput The hidden key is loaded automatically by the hardware on either encryption or decryption at a processor speed of after reset and is not visible to the processor. The 5
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33234H Architecture Overview 20 AMD Geode™ LX Processors Data Book
