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Title Page
IBM PowerPC 750GX and 750GL RISC Micro-
processor
User’s Manual
Version 1.2
March 27, 2006
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® Copyright and Disclaimer © Copyright International Business Machines Corporation 2004, 2006 All Rights Reserved Printed in the United States of America March 2006. The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM POWER PowerPC 750 IBM Logo PowerPC PowerPC Architecture PowerPC Logo IEEE is a registered trademark in the United States, owned by the Institute of Electrical and Electronics Engineers. Other company,
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor List of Figures .............................................................................................................. 13 List of Tables ................................................................................................................ 15 About This Manual ........................................................................................................ 19 Who Should Read This Manual ...................
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2. Programming Model .................................................................................................. 57 2.1 PowerPC 750GX Processor Register Set ....................................................................................... 57 2.1.1 Register Set ........................................................................................................................... 57 2.1.2 PowerPC 750GX-Specific Regist
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.6.1 System Linkage Instructions—OEA ............................................................................. 118 2.3.6.2 Processor Control Instructions—OEA .......................................................................... 118 2.3.6.3 Memory Control Instructions—OEA ............................................................................. 119 2.3.7 Recommended Simplified Mnemonics ...............................
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 4.2 Exception Recognition and Priorities ............................................................................................. 153 4.3 Exception Processing .................................................................................................................... 156 4.3.1 Machine Status Save/Restore Register 0 (SRR0) ............................................................... 156 4.3.2 Machine Status Save/Resto
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.1.8 MMU Instructions and Register Summary ........................................................................... 194 5.2 Real-Addressing Mode .................................................................................................................. 195 5.3 Block-Address Translation ............................................................................................................ 196 5.4 Memory Segment Model
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.6.1.3 Completion-Unit Resource Requirements .................................................................... 237 6.7 Instruction Latency Summary ........................................................................................................ 238 7. Signal Descriptions ................................................................................................. 249 7.1 Signal Configuration ..........................
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.11.4 Time Base Enable (TBEN)—Input ............................................................................. 274 7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)—Input ....................................................... 274 7.2.12 Processor Mode Selection Signals .................................................................................... 274 7.2.13 I/O Voltage Select Signals .......................................
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.6.2 No-DRTRY Mode ................................................................................................................. 318 8.7 Processor State Signals ................................................................................................................ 319 8.7.1 Support for the lwarx and stwcx. Instruction Pair ............................................................... 319 8.7.2 TLBISYNC Input ........
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.1 Performance-Monitor Interrupt .................................................................................................... 349 11.2 Special-Purpose Registers Used by Performance Monitor ......................................................... 350 11.2.1 Performance-Monitor Registers ......................................................................................... 351 11.2.1.1 Monitor Mode Control Register 0 (MM
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 750gx_umTOC.fm.(1.2) March 27, 2006 Page 12 of 377
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor List of Figures Figure 1-1. 750GX Microprocessor Block Diagram .................................................................................. 25 Figure 1-2. L1 Cache Organization .......................................................................................................... 34 Figure 1-3. System Interface ..................................................................................................................
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-5. First Level Address Pipelining ..............................................................................................287 Figure 8-6. Address-Bus Arbitration ........................................................................................................290 Figure 8-7. Address-Bus Arbitration Showing Bus Parking ....................................................................291 Figure 8-8. Address-Bus
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor List of Tables Table 1-1. Architecture-Defined Registers (Excluding SPRs) ................................................................. 42 Table 1-2. Architecture-Defined SPRs Implemented .............................................................................. 43 Table 1-3. Implementation-Specific Registers ......................................................................................... 44 Table 1-4. 750GX Micropr
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-34. SPR Encodings for 750GX-Defined Registers (mfspr) ........................................................112 Table 2-35. Memory Synchronization Instructions—UISA .......................................................................113 Table 2-36. Move-from Time Base Instruction .........................................................................................114 Table 2-37. Memory Synchronization Instructions—V
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 5-7. Table-Search Operations to Update History Bits—TLB Hit Case ........................................ 197 Table 5-8. Model for Guaranteed R and C Bit Settings ......................................................................... 198 Table 6-1. Notation Conventions for Instruction Timing ........................................................................ 214 Table 6-2. Performance Effects of Memory Operand Placemen
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 11-7. HID2 Checkstop Control Bits ................................................................................................362 Table 11-8. L2CR Checkstop Control Bits ...............................................................................................362 List of Tables 750gx_umLOT.fm.(1.2) March 27, 2006 Page 18 of 377
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor About This Manual ® This user’s manual defines the functionality of the PowerPC 750GX and 750GL RISC microprocessors. It describes features of the 750GX and 750GL that are not defined by the architecture. This book is intended as a companion to the PowerPC Microprocessor Family: The Programming Environments (referred to as The Programming Environments Manual). Note: Soft copies of the latest version of this manual and documents
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User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Conventions Used in This Manual Notational Conventions mnemonics Instruction mnemonics are shown in lowercase bold. italics Italics indicate variable command parameters. For example: bcctrx. Book titles in text are set in italics. 0x0 Prefix to denote a hexadecimal number. 0b0 Prefix to denote a binary number. crfD Instruction syntax used to identify a destination Condition Register (CR) field. rA, rB Instruction syntax used to i
