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TMS320C642x DSP
Inter-Integrated Circuit (I2C) Peripheral
User's Guide
Literature Number: SPRUEN0D
March 2011
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2 SPRUEN0D–March 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated
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Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 7 1.1 Purpose of the Peripheral .............................................................................................. 7 1.2 Features ............................................................................
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www.ti.com List of Figures 1 I2C Peripheral Block Diagram............................................................................................. 8 2 Multiple I2C Modules Connected ......................................................................................... 9 3 Clocking Diagram for the I2C Peripheral............................................................................... 10 4 Synchronization of Two I2C Clock Generators During Arbitration .................................
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www.ti.com List of Tables 1 Operating Modes of the I2C Peripheral ................................................................................ 15 2 Ways to Generate a NACK Bit........................................................................................... 16 3 Descriptions of the I2C Interrupt Events................................................................................ 21 4 Inter-Integrated Circuit (I2C) Registers .........................................................
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Preface SPRUEN0D–March 2011 Read This First About This Manual This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices that are compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. The scope of this document assumes that you are familiar with the I2C-bus specification. Notational Convention
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User's Guide SPRUEN0D–March 2011 Inter-Integrated Circuit (I2C) Peripheral 1 Introduction This document describes the operation of the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The scope of this document assumes that you are familiar with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. 1.1 Purpose of the Peripheral The I2C peripheral provides an interface between the TMS320C642x DSP and other devices that are complia
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Introduction www.ti.com 1.3 Functional Block Diagram A block diagram of the I2C peripheral is shown in Figure 1. Refer to Section 2 for detailed information about the architecture of the I2C peripheral. Figure 1. I2C Peripheral Block Diagram I2C peripheral Peripheral data bus ICXSR ICDXR SDA CPU ICRSR ICDRR EDMA Control/status registers Clock SCL synchronizer Prescaler Noise filters Interrupt I2C INT to CPU Sync events to Arbitrator ICREVT ICXEVT EDMA controller 1.4 Industry Standard(s) Complian
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www.ti.com Peripheral Architecture 2 Peripheral Architecture The I2C peripheral consists of the following primary blocks: • A serial interface: one data pin (SDA) and one clock pin (SCL) • Data registers to temporarily hold receive data and transmit data traveling between the SDA pin and the CPU or the EDMA controller • Control and status registers • A peripheral data bus interface to enable the CPU and the EDMA controller to access the I2C peripheral registers • A clock synchronizer to synchron
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Peripheral Architecture www.ti.com 2.2 Clock Generation As shown in Figure 3, PLL1 receives a signal from an external clock source and produces an I2C input clock. A programmable prescaler (IPSC bit in ICPSC) in the I2C module divides down the I2C input clock to produce a prescaled module clock. The prescaled module clock must be operated within the range of 6.7 to 13.3 MHz. The I2C clock dividers divide-down the high (ICCH bit in ICCLKH) and low portions (ICCL bit in ICCLKL) of the prescaled mo
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www.ti.com Peripheral Architecture The prescaler (IPSC bit in ICPSC) must only be initialized while the I2C module is in the reset state (IRS = 0 in ICMDR). The prescaled frequency only takes effect when the IRS bit in ICMDR is changed to 1. Changing the IPSC bit in ICPSC while IRS = 1 in ICMDR has no effect. Likewise, you must configure the I2C clock dividers (ICCH bit in ICCLKH and ICCL bit in ICCLKL) while the I2C module is still in reset (IRS = 0 in ICMDR). 2.3 Clock Synchronization Only one
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Peripheral Architecture www.ti.com 2.4.2 Data Validity The data on SDA must be stable during the high period of the clock (see Figure 5). The high or low state of the data line, SDA, can change only when the clock signal on SCL is low. Figure 5. Bit Transfer on the I2C-Bus Data line stable data SDA SCL Change of data allowed 2.5 START and STOP Conditions The I2C peripheral can generate START and STOP conditions when the peripheral is configured to be a master on the I2C-bus, as shown in Figure 6
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www.ti.com Peripheral Architecture 2.6 Serial Data Formats Figure 7 shows an example of a data transfer on the I2C-bus. The I2C peripheral supports 1-bit to 8-bit data values. Figure 7 is shown in an 8-bit data format (BC = 000 in ICMDR). Each bit put on the SDA line is equivalent to one pulse on the SCL line. The data is always transferred with the most-significant bit (MSB) first. The number of data values that can be transmitted or received is unrestricted; however, the transmitters and recei
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Peripheral Architecture www.ti.com 2.6.2 10-Bit Addressing Format The 10-bit addressing format (Figure 9) is like the 7-bit addressing format, but the master sends the slave address in two separate byte transfers. The first byte consists of 11110b, the two MSBs of the 10-bit slave address, and R/W = 0 (write). The second byte is the remaining 8 bits of the 10-bit slave address. The slave must send acknowledgment (ACK) after each of the two byte transfers. Once the master has written the second b
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www.ti.com Peripheral Architecture 2.7 Endianness Considerations When the device is configured for big-endian mode, in order for the data to be placed in the right side of the register being accessed, access to the I2C registers must be performed as follows: • 8-bit accesses: An offset of 3h must be added to the address of the register being accessed. For example, the offset address of ICDRR becomes 1Bh (18h + 3h). • 16-bit accesses: Not supported for the I2C peripheral. • 32-bit accesses: No of
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Peripheral Architecture www.ti.com 2.9 NACK Bit Generation When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C peripheral sends a NACK bit. Table 2. Ways to Generate a NACK Bit NACK Bit Generation I2C Peripheral Condition Basic Optional Slave-receiver mode Set the NACKM
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www.ti.com Peripheral Architecture 2.10 Arbitration If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitration procedure is invoked. The arbitration procedure uses the data presented on the serial data bus (SDA) by the competing transmitters. Figure 12 illustrates the arbitration procedure between two devices. The first master-transmitter, which drives SDA high, is overruled by another master-transmitter that drives SDA low. The arbitration procedure g
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Peripheral Architecture www.ti.com 2.11 Reset Considerations The I2C peripheral has two reset sources: software reset and hardware reset. 2.11.1 Software Reset Considerations To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All status bits in the I2C interrupt status register (ICSTR) are forced to their default values, and the I2C peripheral remains disabled until IRS is changed to 1. The SDA and SCL pins are in the high-impedance state. NOTE: If
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www.ti.com Peripheral Architecture 2.12.1 Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU The following initialization procedure is for the I2C controller configured in Master Receiver mode. The CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the CPU). 1. Enable I2C clock from the Power and Sleep Controller (see the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8)). 2. Place I2C in reset (clear IRS =
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Peripheral Architecture www.ti.com 4. Enable the desired interrupt you need to receive by setting the desired interrupt bit field within ICIMR to enable the particular Interrupt. • AAS = 1; Expect an interrupt when Master's Address matches yours (ICOAR programmed value). • ICRRDY = 1; Expect a receive interrupt when a byte worth data sent from the master is ready to be read. • ICXRDY = 1; Expect to receive interrupt when the transmit register is ready to be written with a new data that is to be
