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Data
Manual
2001 Digital Audio: Digital Speakers
SLAS307B
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infri
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1 Introduction 1.1 Description The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU 2 2 through the I C slave port or from an external EEPROM through the I C master port. 2 The TAS3002 device also has an integrated 24-bi
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2 • Two I C-selectable, single-ended analog input stereo channels • Equalization bypass mode • Single 3.3-V power supply • Power down without reloading the coefficients • Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz • Master clock frequency of 256f or 512f S S • Can have crystal input to replace MCLK. Crystal input frequency is 256f . S • Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters 1.3 Functional Block Diagram Figure 1−1 is a block dia
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AINRP AINRM Voltage Analog Digital RINA Reference Supplies Supplies RINB AINRP AINRM 24-Bit SDOUT0 AINLP Stereo AINLM ADC LINA AINLP LINB AINLM ALLPASS VCOM INPA AOUTL GPI5 AOUTR GPI4 GPI3 24-Bit GPI2 Stereo DAC GPI1 GPI0 L+R L+R SDOUT2 CS1 32-Bit Audio Signal Processor SDA SCL SDOUT1 32-Bit Audio Signal PWR_DN L R Processor RESET TEST SDATA OSC/CLK PLL Control Select Figure 1−1. TAS3002 Block Diagram 1−3 2 I C Control Controller Control SDIN1 SDIN2 LRCLK/O AV SCLK/O SS(REF) V REFM IFM/S V REFP
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1.4 Terminal Assignments Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each terminal. PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 LINA 1 36 NC V 35 AV 2 DD RFILT 34 NC AV 3 SS(REF) 33 GPI5 AV 4 SS INPA 5 32 GPI4 31 GPI3 RESET 6 30 GPI2 CS1 7 PWR_DN 8 29 GPI1 TEST 28 GPI0 9 27 ALLPASS CAP_PLL 10 SDOUT1 CLKSEL 11 26 MCLKO 12 25 SDOUT0 13 14 15 16 17 18 19 20 21 22 23 24 Figure 1−2. TAS3002 Terminal Assignments 1.5 Terminal Functio
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Table 1−1. TAS3002 Terminal Functions (Continued) TERMINAL I/O I/O DESCRIPTION DESCRIPTION NAME NO. CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL) CLKSEL 11 I Logic low selects 256f ; logic high selects 512f MCLK S S 2 CS1 7 I I C address bit A0; low = 68h, high = 6Ah DV 17 I Digital power supply (3.3 V) DD DV 18 I Digital ground SS GPI0 28 I Switch input terminals GPI1 29 GPI2 30 GPI3 31 GPI4 32 GPI5 33 IFM/S 21 I Digital audio I/O control (low = input; high = output) INPA 5 O Lo
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2 Audio Data Formats 2.1 Serial Interface Formats The TAS3002 device works in master or slave mode. In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and 20 (SCLK/O) becoming outputs to drive slave devices. In the slave
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2.2 Digital Output Modes The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3. 2.2.1 MSB-First, Right-Justified, Serial-Interface Format The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1 shows the following characteristics of this protocol: • Left channel is transmitted when LRCLK is high. • The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK. • The SDOUT(s
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2 2.2.2 I S Serial-Interface Format 2 The normal output mode for the I S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−2 shows the following characteristics of this protocol: • Left channel is transmitted when LRCLK is low. • SDIN is sampled with the rising edge of SCLK. • SDOUT is transmitted on the falling edge of SCLK. • If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets. SCLK LRCLK = f S SDIN X MSB LSB X MSB LSB …… … …… … SDOUT X MSB LS
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2.2.3 MSB-Left-Justified, Serial-Interface Format The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−3 shows the following characteristics of this protocol: • Left channel is transmitted when LRCLK is high. • The SDIN data is justified to the leading edge of the LRCLK. • The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK. SCLK LRCLK = f S SDIN MSB LSB MSB LSB …… …… …… …… SDOUT MSB LS
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2.3 Switching Characteristics PARAMETER MIN TYP MAX UNIT t SCLK cycle time 325.5 ns c(SCLK) t SCLK rising to LRCLK edge 20 ns d(SLR) t SDOUT valid from SCLK falling edge (see Note 1) (1/256f ) + 10 ns d(SDOUT) S t SDIN setup before SCLK rising edge 20 ns su(SDIN) t SDIN hold after SCLK rising edge 100 ns h(SDIN) f LRCLK frequency 32 44.1 48 kHz (LRCLK) Duty cycle 50 % NOTE 1: Maximum of 50-pF external load on SDOUT. t c(SCLK) t r(SCLK) SCLK t f(SCLK) t d(SLR) LRCLK t t d(SLR) d(SDOUT) SDOUT1 SDO
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3 Analog Input/Output The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or 2 B analog input is accomplished by setting a bit in the analog control register (ACR) by an I C command. Additionally, the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC). 3.1 Analog Input Figure 3−1 shows the technique and components required for analog input to the TAS3002 device. The maximum input signal must not exceed 0.7 V . Selection o
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Analog Output (Adjust Capacitors for Desired Low Frequency Response) AOUTR VCOM 24-Bit DAC + 0.1 µF 10 µF AOUTL AGND Figure 3−2. VCOM Decoupling Network 3.2.2 Analog Output With Gain Because the maximum analog output from the TAS3002 device is 0.707 V , the output level can be increased by rms using an external amplifier. The circuit shown in Figure 3−3 boosts the output level to 1 V (when it has a gain of rms 1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers th
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3.2.3 Reference Voltage Filter Figure 3−4 shows the TAS3002 reference voltage filter. 0.1 µF 15 µF 1 µF + + 0.1 µF 0.1 µF 4 3 2 45 V 44 REFP TAS3002 Figure 3−4. TAS3002 Reference Voltage Filter 3−3 AV SS AV SS(REF) V RFILT V REFM
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4 Audio Control/Enhancement Functions 4.1 Soft Volume Update The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute). 2 The volume is adjustable by downloading a gain coefficient through the I C interface in 4.16 format—4 bits for the integer and 16 bits for the fractional part. NO TAG lists the 4.16 coefficients converted into dB for the r
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Left Channel Mix Coefficients SDIN1 ^ SDIN2 ^ ADC 2 I C Register Address 08h = (3) 24-Bit Left Mix Coefficient SDIN1_L Soft L_SUM SDIN2_L 7 Biquad Tone Volume Filters DRCE ADC_L SDOUT1 SDIN1_R Soft SDIN2_R 7 Biquad Tone Volume Filters DRCE ADC_R R_SUM 1/2 SDOUT2 L + R_SUM 1/2 Right Channel Mix Coefficients SDIN1 ^ SDIN2 ^ ADC 2 I C Register Address 07h = (3) 24-Bit Right Mix Coefficient Figure 4−1. TAS3002 Mixer Function 4.4 Mono Mixer Control The TAS3002 device contains a second mixer that perf
