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TMS320DM644x DMSoC
Multimedia Card (MMC)/Secure Digital (SD)
Card Controller
User's Guide
Literature Number: SPRUE30B
September 2006
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2 SPRUE30B–September 2006 Submit Documentation Feedback
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Contents Preface ............................................................................................................................... 7 1 Introduction................................................................................................................ 9 1.1 Purpose of the Peripheral....................................................................................... 9 1.2 Features.............................................................................................
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4.13 MMC Command Register (MMCCMD) ...................................................................... 52 4.14 MMC Argument Register (MMCARGHL).................................................................... 54 4.15 MMC Response Registers (MMCRSP0-MMCRSP7)...................................................... 55 4.16 MMC Data Response Register (MMCDRSP)............................................................... 57 4.17 MMC Command Index Register (MMCCIDX)..............................
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List of Figures 1 MMC/SD Card Controller Block Diagram ............................................................................... 10 2 MMC/SD Controller Interface Diagram .................................................................................. 11 3 MMC Configuration and SD Configuration Diagram................................................................... 11 4 MMC/SD Controller Clocking Diagram ..................................................................................
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List of Tables 1 MMC/SD Controller Pins Used in Each Mode.......................................................................... 13 2 MMC/SD Mode Write Sequence ......................................................................................... 14 3 MMC/SD Mode Read Sequence ......................................................................................... 15 4 Description of MMC/SD Interrupt Requests ............................................................................ 27
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Preface SPRUE30B–September 2006 Read This First About This Manual This manual describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide removable data storage. The MMC/SD controller provides an interface to external MMC and SD cards. The MMC/SD protocol performs the communication between the MMC/SD controller and MMC/SD card(s). Notational Conventions This docume
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www.ti.com Related Documentation From Texas Instruments SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRAAA6 —EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating from the Texas Instruments TMS320C
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User's Guide SPRUE30B–September 2006 Multimedia Card (MMC)/Secure Digital (SD) Card Controller 1 Introduction This document describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). 1.1 Purpose of the Peripheral A number of applications use the multimedia card (MMC)/secure digital (SD) card to provide removable data storage. The MMC/SD card controller provides an interface to external MMC and SD cards. The communication betw
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www.ti.com Peripheral Architecture Figure 1. MMC/SD Card Controller Block Diagram ARM CPU MMC/SD interface MMC/SD card interface Status DMA requests CLK and divider Interrupts registers FIFO 1.4 Supported Use Case Statement The MMC/SD card controller supports the following user cases: • MMC/SD card identification • MMC/SD single-block read using CPU • MMC/SD single-block read using EDMA • MMC/SD single-block write using CPU • MMC/SD single-block write using EDMA • MMC/SD multiple-block read usin
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www.ti.com Peripheral Architecture Figure 2. MMC/SD Controller Interface Diagram MMCs or SD cards ARM MMC/SD controller Native signals CMD Native packets DAT0 or DAT0−3 CLK Memory EDMA Figure 3. MMC Configuration and SD Configuration Diagram MMC/SD configuration MMC/SD controller MMC and SD (1−bit mode) SD_CLK CLK SD_CMD CMD SD_DATA0 DAT0 SD_DATA1 SD_DATA2 SD_DATA3 SD configuration MMC/SD controller SD card (4−bit mode) SD_CLK CLK SD_CMD CMD SD_DATA0 DAT0 SD_DATA1 DAT1 SD_DATA2 DAT2 SD_DATA3 DAT
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www.ti.com Peripheral Architecture 2.1 Clock Control There are two clocks, the function clock and the memory clock, in the MMC/SD controller (Figure 4). The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD card(s). The MMC/SD controller is capable of operating with a function clock up to 100 MHz. The memory clock appears on the SD_CLK pin of the MMC/SD controller interface. The memory clock controls the timing of communication betw
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www.ti.com Peripheral Architecture 2.2 Signal Descriptions Table 1 shows the MMC/SD controller pins that each mode uses. The MMC/SD protocol uses the clock, command (two-way communication between the MMC controller and memory card), and data (DAT0 for MMC card, DAT0-3 for SD card) pins. Table 1. MMC/SD Controller Pins Used in Each Mode Function MMC and SD (1-bit mode) SD (4-bit mode) (1) Pin Type Communications Communications CLK O Clock line Clock line CMD I/O Command line Command line DAT0 I/O
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www.ti.com Peripheral Architecture Figure 5. MMC/SD Mode Write Sequence Timing Diagram CMD Busy 2 CRC bytes low Data Start End Start End bit bit bit bit CLK Table 2. MMC/SD Mode Write Sequence Portion of the Sequence Description WR CMD Write command: A 6-byte WRITE_BLOCK command token is sent from the ARM to the card. CMD RSP Command response: The card sends a 6-byte response of type R1 to acknowledge the WRITE_BLOCK to the ARM. DAT BLK Data block: The ARM writes a block of data to the card. The
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www.ti.com Peripheral Architecture Figure 6. MMC/SD Mode Read Sequence Timing Diagram CMD 1 transfer 2 CRC source bit bytes Data Start End bit bit CLK Table 3. MMC/SD Mode Read Sequence Portion of the Sequence Description RD CMD Read command: A 6-byte READ_SINGLE_BLOCK command token is sent from the ARM to the card. CMD RSP Command response: The card sends a response of type R1 to acknowledge the READ_SINGLE_BLOCK command to the ARM. DAT BLK Data block: The card sends a block of data to the ARM.
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www.ti.com Peripheral Architecture A high-level operational description is as follows: • Data is written to the FIFO through the MMC data transmit register (MMCDXR). Data is read from the FIFO through the MMC data receive register (MMCDRR). This is true for both the CPU and EDMA driven transactions; however, for the EDMA transaction, the EDMA access to the FIFO is transparent. • The ACCWD bits in the MMC FIFO control register (MMCFIFOCTL) determines the behavior of the FIFO full (FIFOFUL) and FI
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www.ti.com Peripheral Architecture 2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) The CPU or EDMA controller can read 32 bits at a time from the FIFO by reading the MMC data receive register (MMCDRR) and write 32 bits at a time to the FIFO by writing to the MMC data transmit register (MMCDXR). However, since the memory card is an 8-bit device, it transmits or receives one byte at a time. Figure 8 and Figure 9 show how the data-size difference is handled by the data registers in little-e
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www.ti.com Peripheral Architecture Figure 9. Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA 3 0 1st 1st 2nd 3rd 4th 2nd 3rd 4th Support byten = ”1111” 3 0 1st 1st 2nd 3rd 2nd 3rd Support byten = ”1110” 3 0 1st 1st 2nd 2nd Support byten = ”1100” 3 0 1st 1st Support byten = ”1000” 18 Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUE30B–September 2006 Submit Documentation Feedback
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www.ti.com Peripheral Architecture 2.6 FIFO Operation During Card Read Operation 2.6.1 EDMA Reads The FIFO controller manages the activities of reading the data in from the card and issuing EDMA read events. Each time an EDMA read event is issued, an EDMA read request interrupt generates. Figure 10 provides details of the FIFO controllers operation. As data is received from the card, it is read into the FIFO. When the number of bytes of data received is equal to the level set by the FIFOLEV bits
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www.ti.com Peripheral Architecture Figure 10. FIFO Operation During Card Read Diagram FIFO Check1/Start FIFO Yes full ? No Capture data, no DMA pending Increment counter No Counter =FIFOLEV ? Yes Generate DMA Reset counter FIFO check 2 FIFO Yes full ? No Capture data, DMA Increment counter Idle, DMA pending Counter Yes =FIFOLEV DMA No ? done ? No Yes DMA Generate DMA No done ? Reset counter Yes 20 Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUE30B–September 2006 Submit Documentat
