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ADS5525/27/45/46/47 EVM User
Guide
User's Guide
November 2006
SLWU028B
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2 SLWU028B–January 2006–Revised November 2006 Submit Documentation Feedback
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Contents 1 Overview.................................................................................................................... 5 1.1 EVM Basic Functions............................................................................................ 5 2 EVM Quick Start Guide ................................................................................................ 6 2.1 EVM LVDS Output Mode Quick Start (Default) .............................................................. 6 2.2 EVM C
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List of Figures 1 ADS5547 SNR Performance vs Decoupling ............................................................................. 8 2 THS4509 + ADS5545 EVM Performance ................................................................................ 9 3 Eye Diagram of Data on Header J4...................................................................................... 11 4 Top Layer..............................................................................................................
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User's Guide SLWU028B–January 2006–Revised November 2006 1 Overview This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating the performance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in evaluation of the many features of the ADCs and the performance of the device der many conditions. 1.1 EVM Basic Functions Analog input to the ADC is provided via external SMA connectors. The user supplies a single-ended input, wh
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www.ti.com EVM Quick Start Guide 2 EVM Quick Start Guide The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems. Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode or CMOS output mode. Note: Follow the steps in the listed order; not doing so could result in improper operation. 2.1 EVM LVDS Output Mode Quick Start (Default) 1. Ensure a jumper is installed between pins 1 and 2 on JP2. 2. Ensure DIP switch
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www.ti.com Circuit Description 3 Circuit Description 3.1 Schematic Diagram The schematic diagram for the EVM is in Section 5.3 of this document. 3.2 Circuit Function The following paragraphs describe the function of individual circuits. See the data sheet for complete device operating characteristics. 3.2.1 Configuration Options The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is configured for parallel-mode operation. Table 1 describes the functionality
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www.ti.com Circuit Description Table 2. EVM Power Options BANANA JACK NAME VOLTAGE DESCRIPTION J9 Device AGND GND J10 AGND GND J11 Device AVDD 3.3 Device analog supply J12 Amplifier negative –5 THS4509 Vs– supply rail J13 Amplifier positive rail 5 THS4509 Vs+ supply J14 Auxiliary power 5 Supplies power to all peripheral circuitry including the FPGA and PROM. Voltages rails are created by using TI's TPS75003 voltage regulator. J15 Device DVDD 3.3 Device internal digital output supply J16 DGND GND
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www.ti.com Circuit Description The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter with a cutoff frequency of 70 MHz. Figure 2 shows the performance of the ADS5545 using the THS4509 path. 10 1 0 −10 −20 −30 −40 −50 −60 −70 5 −80 3 x −90 4 −100 2 −110 −12
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www.ti.com Circuit Description Table 3. Output Connector J4 J4 PIN ADS5525/27 DESCRIPTION ADS5545/46/47 DESCRIPTION 1 CLK CLK 2 GND GND 3 NC NC 4 GND GND 5 Reserved Reserved 6 GND GND 7 Reserved Reserved 8 GND GND 9 NC Data bit 0 (LSB) 10 GND GND 11 NC Data bit 1 12 GND GND 13 Data bit 0 (LSB) Data bit 2 14 GND GND 15 Data bit 1 Data bit 3 16 GND GND 17 Data bit 2 Data bit 4 18 GND GND 19 Data bit 3 Data bit 5 20 GND GND 21 Data bit 4 Data bit 6 22 GND GND 23 Data bit 5 Data bit 7 24 GND GND 25
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www.ti.com Circuit Description C001 Figure 3. Eye Diagram of Data on Header J4. 3.2.6 Test Points For added EVM visibility and control, several test points are provided. Table 4 summarizes the test points available. SLWU028B–January 2006–Revised November 2006 11 Submit Documentation Feedback
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www.ti.com Circuit Description Table 4. Test Points TP DESCRIPTION TP1 ADC common mode, input or output depending on the setting of SW1, switch 4 TP3 THS4509 power down TP4 ADC output enable TP5 AGND TP6 AGND TP7 AGND TP8 DGND TP9 FPGA M0 pin; determines which FPGA logic file to load TP10 ADC SCLK TP11 TPS75003 1.2 enable TP12 TPS75003 2.5 enable TP13 TPS75003 3.3 enable 3.2.7 LED Operation To give greater visibility into the EVM operations, two LEDs are provided, D3 and D4. On power up, D4 is a
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www.ti.com Expansion Options 4 Expansion Options The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmost flexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need to develop a custom prototype board. 4.1 Custom FPGA Code Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA, rapidly speeding up digital development time. This allows the flexibility of prot
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www.ti.com Physical Description 5 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM. 5.1 PCB Layout The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 4 through Figure 9. The layout features split analog and digital ground planes; however, similar performance can be had with careful layout using a single ground plane. Users can connect the analog and digital ground planes undern
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www.ti.com Physical Description K002 Figure 5. Layer 2, Ground Plane SLWU028B–January 2006–Revised November 2006 15 Submit Documentation Feedback
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www.ti.com Physical Description K003 Figure 6. Layer 3, Power Plane #1 16 SLWU028B–January 2006–Revised November 2006 Submit Documentation Feedback
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www.ti.com Physical Description K004 Figure 7. Layer 4, Power Plane #2 SLWU028B–January 2006–Revised November 2006 17 Submit Documentation Feedback
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www.ti.com Physical Description K005 Figure 8. Layer 5, Ground Plane 18 SLWU028B–January 2006–Revised November 2006 Submit Documentation Feedback
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www.ti.com Physical Description K006 Figure 9. Layer 6, Bottom Layer SLWU028B–January 2006–Revised November 2006 19 Submit Documentation Feedback
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www.ti.com Physical Description 5.2 Bill of Materials 20 SLWU028B–January 2006–Revised November 2006 Submit Documentation Feedback
