Instruction d'utilisation Motorola MPC750

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MPC750UMAD/AD
1/1999
Rev. 1
ª
Errata to
MPC750 RISC Microprocessor UserÕs
Manual
This errata describes corrections to the MPC750 RISC Microprocessor
UserÕs Manual. These corrections also apply to the MPC740, which is
described in MPC750 RISC Microprocessor UserÕs Manual. For
convenience, the section number and page number of the errata item in the
userÕs manual are provided.
To locate any published updates for this document, refer to the world-wide
web at http://www.mot.com/powe

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1 DBP Disable 60x bus address and data parity generation. 0 The system generates address and data parity. 1 Parity generation is disabled and parity signals are driven to 0 during bus operations. When parity generation is disabled, all parity checking should also be disabled and parity signals need not be connected. Replace the description of HID0[BTIC] (bit 26), with the following: 26 BTIC BTIC enable. Used to enable use of the 64-entry branch instruction cache. 0 The BTIC conten

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5.1.7, 5-18 Table 5-4, delete the second row in table (lwarx or stwcx. with W = 1). 7.2.5.2.1, 7-14 For ARTRY, change ÒTiming Comments,Ó ÒNegation,Ó Þrst paragraph, last sentence to the following: First the buffer goes to high impedance for a minimum of one-half processor cycle (dependent on the clock mode), then it is driven negated for one-half bus cycle before returning to high impedance. 9.1.2, 9-5 In Table 9-1, replace the description of L2CR[L2DO] (bit 9), with the followi

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The PowerPC name is a registered trademark and the PowerPC logotype is a trademark of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. Mfax is a trademark of Motorola, Inc. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integr