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82543GC Gigabit Ethernet Controller
Specification Update
June 18, 2004
Revision 2.1
The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate
from published specifications. Current characterized errata are documented in this Specification Update.
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82543GC Gigabit Ethernet Controller Specification Update Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
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82543GC Gigabit Ethernet Controller Specification Update CONTENTS CONTENTS .........................................................................................................................................................3 REVISION HISTORY...........................................................................................................................................5 PREFACE....................................................................................................
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82543GC Gigabit Ethernet Controller Specification Update 27. Link Status Change Interrupt Only Occurs If Link is Up ....................................................................17 28. Early Transmit Feature Does Not Operate Correctly.........................................................................17 29. TDO Output Not Floated When JTAG TAP Controller Inactive .........................................................18 30. Initialization Ignores Incorrect EEPROM Signature......
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82543GC Gigabit Ethernet Controller Specification Update REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Date of Revision Revision Description June 18, 2004 2.1 Initial Public Release 5
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82543GC Gigabit Ethernet Controller Specification Update Note: This page is intentionally left blank. 6
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82543GC Gigabit Ethernet Controller Specification Update PREFACE This document is an update to published specifications. There are two current specification documents: • 82543GC Gigabit Ethernet Controller Datasheet, Intel Corporation. • OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual, Intel Corporation. This document is intended for hardware system manufactures and software developers of applications, operating systems or tools. It contains Specification Changes, Errata,
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82543GC Gigabit Ethernet Controller Specification Update GENERAL INFORMATION This section covers the 82543GC device. 82543GC COMPONENT MARKING INFORMATION Stepping QDF S- Spec Top Marking Notes Number Number Engineering Samples. May be marked with either QDF A0 Q415 S L3N8 FW82543GC number or S-spec number. Engineering Samples. May be marked with either QDF A1 Q416 S L3N9 FW82543GC number or S-spec number. Engineering Samples. May be marked two ways: with the A2 Q417 N/A FW82543
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82543GC Gigabit Ethernet Controller Specification Update Summary Table of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed 82543GC steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations: CODES USED IN SUMMAR
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82543GC Gigabit Ethernet Controller Specification Update 26 X X X NoFix Default Speed Selection May Depend on EEPROM Presence 15 27 X X X NoFix Link Status Change Interrupt Only Occurs If Link is Up 15 28 X X X NoFix Early Transmit Feature Does Not Operate Correctly 15 29 X X X NoFix TDO Output Not Floated When JTAG TAP Controller Inactive 16 30 X X X NoFix Initialization Ignores Incorrect EEPROM Signature 16 31 X X X NoFix Internal Loopback Difficulties 16 32 X X X NoFix Collision
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82543GC Gigabit Ethernet Controller Specification Update SPECIFICATION CHANGES 1. GMII Setup and Hold Times Problem: The data sheet contains incorrect setup and hold time specifications for the GMII interface. The old setup and hold times were 2.5ns minimum and 4ns. typical. For the receive signals, the new setup time is 2.0ns. (min.) the new hold time is 0ns. (min.). For the transmit signals, the new setup time is 2.5ns. (min.) and the new hold time is 0.5ns. (min.) Documentation w
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82543GC Gigabit Ethernet Controller Specification Update Workaround: None. Status: This erratum was resolved in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 4. Some Registers Cannot Be Accessed During Reset Problem: PCI accesses to transmit descriptor registers will not succeed if the 82543GC controller is in a transmit reset state. Similarly, PCI accesses to receive descriptor registers will not succeed if the 82543GC controller is in a receive reset state. Affected re
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82543GC Gigabit Ethernet Controller Specification Update Implication: Data transfer performance is substantially reduced due to error packets. Workaround: None. Status: Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 8. 48 Bit Preambles Sent in 10Mb and 100Mb Operation Problem: The 82543GC device transmits 48 bit preambles instead of 56 bit preambles for 10Mb and 100Mb operation. Implication: Certain 10Mb and 100Mb repeaters will only
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82543GC Gigabit Ethernet Controller Specification Update Workaround: None. Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 13. Zero-Byte PCI Bus Writes Problem: The 82543GC Gigabit Ethernet Controller can generate zero-byte writes on a 32-bit PCI bus because it is has a 64-bit internal architecture. A zero-byte access is defined as a data transfer with IRDY# and TRDY# asserted but none of the byte enables asse
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82543GC Gigabit Ethernet Controller Specification Update Workaround: When using half-duplex mode, program the 82543GC Gigabit Ethernet Controller for a very high collision threshold and allow it to retransmit packets that encounter a late collision. Also, if the “early transmit” feature is used, configure the device to retransmit packets that encounter underruns. Status: Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 17. Flash Memory Address
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82543GC Gigabit Ethernet Controller Specification Update When the size of a received packet exceeds the space in the packet buffer memory, the 82543GC Gigabit Ethernet Controller will drop the packet. This behavior is normal and is not affected by the erratum. Implication: Software cannot directly access packet buffer memory. Such accesses are typically performed only for diagnostic purposes. Workaround: It may not be possible to prevent the problem, requiring software to screen for pac
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82543GC Gigabit Ethernet Controller Specification Update Problem: Bits SWDPIO_EXT[7:4] of Initialization Control Word 2 in the EEPROM are supposed to map to bits SWDPIOHI[11:8] in the Extended Device Control Register at offset 0x00018. Instead, the bits map to SWDPINSHI[7:4] of that register. Implication: The input/output characteristic of some of the software-defined pins could be assigned incorrectly. Workaround: Program these bits in the Extended Device Control Register correctly in
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82543GC Gigabit Ethernet Controller Specification Update Problem: Use of the early transmit function may cause hangs in 10/100 Mb/s operation. Implication: The early transmit feature is only applicable to 10/100 Mbps operation, where it was expected to improve overall data transfer rates. With the feature enabled, the 82543GC controller may lock up or exhibit other problems; insignificant performance gains were observed. Workaround: None. Do not use the early transmit function. Status:
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82543GC Gigabit Ethernet Controller Specification Update Problem: Asserting the collision input signal (COL) can cause the transmitter to hang intermittently in TBI mode. Implication: When the 82543GC Gigabit Ethernet Controller is in TBI mode, the collision signal is meaningless because receive and transmit channels each have their own dedicated optical fibers. Nevertheless, the pin must be tied off carefully. Workaround: For TBI mode operation, use a pulldown resistor on the COL inp
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82543GC Gigabit Ethernet Controller Specification Update Implication: Corrupted descriptor writebacks may include writing back unconsumed descriptors, descriptor writebacks to incorrect addresses, or writebacks missed altogether. In addition, the device may cease to access the PCI bus or cease packet transmission. If the device hangs, a full software or hardware reset is needed. Workaround: Leave WTHRESH at its default value of 0. Descriptors will be written back immediately. Status: I
