Resumen del contenido incluido en la página 1
Evaluation Board User Guide
UG-001
One Technology Way • P.O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the AD9272/AD9273 for Ultrasound Systems
FEATURES DOCUMENTS NEEDED
Full featured evaluation board for the AD9272/AD9273 AD9272 and AD9273 data sheets
SPI and alternate clock options HSC-ADC-EVALCZ data sheet, High Speed Converter
Internal and external reference options Evaluation Platform (FPGA-based data capture
Resumen del contenido incluido en la página 2
UG-001 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Default Operation and Jumper Selection Settings ....................5 Equipment Needed ........................................................................... 1 Evaluation Board Software Quick Start Procedures .....................7 Documents Needed .......................................................................... 1 Co
Resumen del contenido incluido en la página 3
Evaluation Board User Guide UG-001 EVALUATION BOARD HARDWARE The AD9272/AD9273 evaluation board provides all of the support evaluation board using the SPI and alternate clock options, a circuitry required to operate the AD9272/AD9273 in its various separate 3.3 V analog supply is needed in addition to the other modes and configurations. Figure 2 shows the typical bench supplies. The 3.3 V supply, or AVDD_3P3V, should have a 1 A characterization setup used to evaluate the ac performance of
Resumen del contenido incluido en la página 4
UG-001 Evaluation Board User Guide WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY 6V DC 2A MAX SIGNAL SYNTHESIZER 6V DC 2A MAX ANALOG INPUT SPECTRUM ANALYZER CW OUTPUT PC RUNNING ADC ANALYZER AGILENT OR VISUAL ANALOG POWER SUPPLY USER SOFTWARE SIGNAL SYNTHESIZER OPTIONAL CLOCK SOURCE GAIN CONTROL INPUT Figure 2. Evaluation Board Connection Rev. 0 | Page 4 of 24 07782-070
Resumen del contenido incluido en la página 5
Evaluation Board User Guide UG-001 PDWN DEFAULT OPERATION AND JUMPER SELECTION SETTINGS To enable the power-down feature, short P303 to the on position (AVDD) on the PDWN pin. This section explains the default and optional settings or modes allowed on the AD9272/AD9273 Rev. A evaluation board. STBY To enable the standby feature, short P302 to the on position Power Circuitry (AVDD) on the STBY pin. Connect the switching power supply that is supplied in the evaluation kit between a ra
Resumen del contenido incluido en la página 6
UG-001 Evaluation Board User Guide between the AD9272/AD9273 CWDx± outputs and the AD8339 inputs. DOUTx+, DOUTx− If an alternative data capture method to the setup described in Figure 2 is used, optional receiver terminations, R701 to R710, can be installed next to the high speed backplane connector. Rev. 0 | Page 6 of 24
Resumen del contenido incluido en la página 7
Evaluation Board User Guide UG-001 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9272/ AD9273 either on the evaluation board or in a system level design. Both the default and optional settings are described. CONFIGURING THE BOARD Before using the software for testing, configure the evaluation board as follows: 1. Connect the evaluation board to the data capture board as shown in Figure 1 and Figure 2. 2. Connect one 6 V,
Resumen del contenido incluido en la página 8
UG-001 Evaluation Board User Guide Setting Up the SPI Controller COLLAPSE DISPLAY BUTTON After the ADC data capture board setup is completed, set up the SPI Controller using the following procedure: SETTINGS BUTTON 1. Open the SPI Controller software by going to the Start menu or double-clicking the SPI Controller software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded.
Resumen del contenido incluido en la página 9
Evaluation Board User Guide UG-001 5. In the ADC A tab of SPI Controller, find the OFFSET(10) box. Use the drop-down box labeled Offset Adj to perform an offset correction to the LNA if the LNA power setting BIAS_CURR_A(12) has been set low. The default value is 32. Select 33 if the low LNA power setting BIAS_CURR_A(12) is used. Figure 12. SPI Controller, OFFSET(10) Box Figure 10. SPI Controller, CHIP GRADE(2) Box 4. In the ADCBase 0 tab of the SPI Controller, find the HIGHPASS(2B
Resumen del contenido incluido en la página 10
UG-001 Evaluation Board User Guide 0 Adjusting the Amplitude of the Input Signal f = 3.5MHz @ –1dBFS IN –10 LNA = 6× Next, adjust the amplitude of the input signal for each channel V = 1V –20 GAIN FILTER TUNED as follows: –30 HPF = 700kHz –40 1. Adjust the amplitude of the input signal so that the –50 fundamental is at the desired level. (Examine the Fund –60 Power reading in the left panel of the VisualAnalog FFT –70 window.) If the gain pin voltage is too low, it is not possible –80 to
Resumen del contenido incluido en la página 11
Evaluation Board User Guide UG-001 Figure 19. SPI Controller, CROSSPOINT SWITCH(2D) Box 8. Examine the spectrum analyzer for the CW Doppler output (see Figure 20 for an example). 0 –10 FREQUENCY = 2.3MHz –20 CWD1±, DIFFERENTIAL OUTPUT –30 –40 –50 –60 –70 –80 –90 –100 02 510 15 205 FREQUENCY (MHz) Figure 20. Typical Spectrum Analyzer Display of CWD Output Figure 18. SPI Controller, MODES(8) Box 7. In the ADC x tab of the SPI Controller, where x is the channel to which an analog
Resumen del contenido incluido en la página 12
UG-001 Evaluation Board User Guide EVALUATION BOARD SCHEMATICS AND ARTWORK Figure 21. Evaluation Board Schematic, DUT Analog Input Circuits Rev. 0 | Page 12 of 24 07782-005
Resumen del contenido incluido en la página 13
Evaluation Board User Guide UG-001 Figure 22. Evaluation Board Schematic, DUT Analog Input Circuits (Continued) Rev. 0 | Page 13 of 24 07782-006
Resumen del contenido incluido en la página 14
UG-001 Evaluation Board User Guide Figure 23. Evaluation Board Schematic, DUT, VREF, and Decoupling Rev. 0 | Page 14 of 24 07782-007
Resumen del contenido incluido en la página 15
Evaluation Board User Guide UG-001 Figure 24. Evaluation Board Schematic, Clock, SPI, and Gain Circuits Rev. 0 | Page 15 of 24 07782-008
Resumen del contenido incluido en la página 16
UG-001 Evaluation Board User Guide Figure 25. Evaluation Board Schematic, Power Supply, CW Doppler, Digital Output Interface Rev. 0 | Page 16 of 24 07782-009
Resumen del contenido incluido en la página 17
Evaluation Board User Guide UG-001 Figure 26. Evaluation Board Layout, Top Side Rev. 0 | Page 17 of 24 07782-010
Resumen del contenido incluido en la página 18
UG-001 Evaluation Board User Guide Figure 27. Evaluation Board Layout, Ground Plane (Layer 2) Rev. 0 | Page 18 of 24 07782-011
Resumen del contenido incluido en la página 19
Evaluation Board User Guide UG-001 Figure 28. Evaluation Board Layout, Power Plane (Layer 3) Rev. 0 | Page 19 of 24 07782-012
Resumen del contenido incluido en la página 20
UG-001 Evaluation Board User Guide Figure 29. Evaluation Board Layout, Power Plane (Layer 4) Rev. 0 | Page 20 of 24 07782-013
