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AMD Geode™ GX Processor/
CS5535 Companion Device
GeodeROM Porting Guide
April 2006
Publication ID: 32430C
AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
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© 2006 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property
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Contents 32430C Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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32430C Contents 4 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
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List of Figures 32430C List of Figures Figure 3-1. GeodeLink™ Architecture Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4-1. Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7-1. GLIU Descriptor Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7-2. CPU Core Cache Des
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32430C List of Figures 6 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
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List of Tables 32430C List of Tables Table 4-1. Default Region Configuration Properties Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4-2. Diverse Device I/O Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide 7
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32430C List of Tables 8 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
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Overview 32430C 1.0Overview 1 1.1 Introduction This document describes the changes needed for GeodeROM and other BIOSs to support the AMD Geode™ GX proces- sor and the AMD Geode™ CS5535 companion device. GeodeROM requires modifications for hardware initialization and specific implementations. Each section targets the GeodeROM changes needed to support the GX processor/CS5535 device system. Where appro- priate, the changes list the “Entry Conditions” that briefly describe the machine state requir
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32430C Assumption 10 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
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Model Specific Registers 32430C 2.0Model Specific Registers 2 There are two ways to read or write Model Specific Registers (MSRs) in a Geode™ GX processor system. Software run- ning on the processor can use the RDMSR and WRMSR instructions, and modules within the processor can use the 2 GeodeLink™ MSR transactions. The second method allows debug modules, such as the System Navigator from FS (First Silicon Solutions), to program MSRs. All MSRs are 64 bits wide. The MSR addresses are 32 bits, whe
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32430C Model Specific Registers 12 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
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GeodeLink™ Architecture 32430C 3.0GeodeLink™ Architecture 3 GeodeLink™ architecture connects the internal modules of the AMD Geode™ GX processor using the data channels pro- vided by GeodeLink Interface Units (GLIUs). GeodeLink modules are connected to GLIU ports 1 – 7 as shown in Figure 3- 1. Port 0 is always the GLIU itself. GLIUs can be chained together and up to a maximum of six GLIUs can be connected allowing for 32 modules. GLMC 1 CPU Core 3 0 7 4 Not Used DC GLIU0 6 5 VP GP 2 GLIU0 GLIU1
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32430C GeodeLink™ Architecture 3.1 GeodeLink™ MSR Addressing The GX processor’s MSRs are addressed from the source module to the port of the target module. The topology of the GX processor must be understood to derive the address. An MSR address is parsed into two fields, the port address (18 bits) and the index (14 bits). The port address is further parsed into six 3-bit channel address fields. Each 3-bit field represents, from the perspective of the source module, the GLIU channels that are us
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Initialization 32430C 4.0Initialization 4 4.1 Processor Initialization The AMD Geode™ GX processor contains many of the components normally found in system support chipsets. GeodeROM must set up these components, including the DRAM controller, L1 cache controller, clock control, and PCI con- troller as well as some proprietary systems like GeodeLink™ architecture. This chapter contains descriptions and some pseudo code for GX processor-specific code sequences in GeodeROM. The modifications are g
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32430C Initialization 4.1.2 Calculating Processor Speed Entry Conditions: Stack and No-Stack versions required. 8254 timer available (port 61). Procedure: � Utilize the Real Time Stamp Counter (RTSC). � Disable the L1 cache. � Set up a channel of the 8254 Timer chip to count for a predetermined amount of time. � Read the CPU RTSC and save the initial count value. � Poll counter and wait for it to roll over. � Read the CPU RTSC and save as the final count. � Subtract the initial value of the RTSC
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Initialization 32430C 4.1.3.1 Size Memory Entry Conditions: 4 GB descriptor in FS Core register. Procedure: For each DIMM: � Set the following in the MC_CF07_DATA register MSR Address 20000018h): — Module Banks per DIMM – SPD byte 5: Number of DIMM Banks — Banks per SDRAM device – SPD byte 17: Number of Banks on SDRAM device — DIMM size - Size = Density * Banks – SPD byte 5: Number of DIMM Banks – SPD byte 31: Module Bank Density — Page size - Page size = 2^# Column Addresses – SPD byte 4: Numbe
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32430C Initialization 4.1.5.1 GLIU Descriptors Initialization Register: P2D_BM, P2D_BMO, P2D_R, P2D_RO, P2D_SC (GLIU0 MSR Address 10000020h-1000003Fh, GLIU1 MSR Address 40000020h-1000003Fh) IO_BM, IO_SC (GLIU0 MSR Address 100000E0h-100000FFh, GLIU1 MSR Address 400000E0h-400000FFh) Set up system memory map with GeodeLink Descriptors and Region Control Registers (RConfs). Descriptors and RConfs must match each other. These register maps will look like the memory map from INT 15h AX = E820. The re
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Initialization 32430C Registers: CR0 RCONF MSRs: CPU Core MSR Address 00001808h-00001817h Instruction Memory Configuration Register: CPU Core MSR Address 00001700h Data Memory Configuration Register: CPU Core MSR Address 00001800h Entry Conditions: None Procedure: IF Setup the Default Region Configuration Properties and any other RCONFs required. Write Cache Disable and Not Write-Through bits (bits [30:29]) in the CR0 register. WBINVD ENDIF Note: See Figure 7-2 on page 31
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32430C Initialization 4.2 AMD Geode™ CS5535 Companion Device Initialization The Geode™ CS5535 is a complete companion device to the GX processor. The Geode CS5535 incorporates the GeodeLink technology developed in the GX processor to make a transparent GeodeLink through the PCI to the CS5535 device. The CS5535 companion device contains many of the components normally found on the SuperI/O chip. GeodeROM and VSA2 technology initialize these components, including the hard disk controller, USB cont
