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SP605 Hardware
User Guide
[Guide Subtitle]
[optional]
UG5 UG526 ( 26 (v1. v1.1 1. .1 1) ) Feb Febr ruary 1, uary 1, 20 2010 [ 10 optional]
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any li
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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 1: SP605 Evaluation Board Overview . . . . . . . .
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System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High) . . . . . . . . . . 48 Mode DIP Switch SW1 (Active-High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18. VITA 57.1 FMC LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC Adapter and 12V Input Power Jack/Switch
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Preface About This Guide This manual accompanies the Spartan®-6 FPGA SP605 Evaluation Board and contains information about the SP605 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “SP605 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the SP605 board. • Appendix A, “Default Jumper and Switch Settings.” • Appendix B, “VITA 57.1 FMC LPC Connector Pinout.” • Appendix C, “SP6
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Preface: About This Guide This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs. • Spartan-6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device block RAM capabilities. • Spartan-6 FPGA GTP Transceivers User Guide This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs. • Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and
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Chapter 1 SP605 Evaluation Board Overview The SP605 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX45T-3FGG484 FPGA. The SP605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 component memory, a 1-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O and a UART. Additional user desired features can be added through mezzanine cards attached to the on
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Chapter 1: SP605 Evaluation Board Features The SP605 board provides the following features: • 1. Spartan-6 XC6SLX45T-3FGG484 FPGA • 2. 128 MB DDR3 Component Memory • 3. SPI x4 Flash • 4. Linear BPI Flash • 5. System ACE CF and CompactFlash Connector • 6. USB JTAG • 7. Clock Generation ♦ Fixed 200 MHz oscillator (differential) ♦ Socket with a 2.5V 27MHz oscillator (single-ended) ♦ SMA connectors (differential) ♦ SMA connectors for MGT clocking (differential) • 8. Multi-Gigabit Transceivers (GTP M
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Overview • 17. Switches ♦ Power On/Off slide switch ♦ System ACE CF Reset pushbutton ♦ System ACE CF bitstream image select DIP switch ♦ Mode DIP switch • 18. VITA 57.1 FMC LPC Connector • Configuration Options ♦ 3. SPI x4 Flash (both onboard and off-board) ♦ 4. Linear BPI Flash ♦ 5. System ACE CF and CompactFlash Connector ♦ 6. USB JTAG • Power Management ♦ AC Adapter and 12V Input Power Jack/Switch ♦ Onboard Power Regulation Block Diagram Figure 1-1 shows a high-level block diagram of the SP6
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Chapter 1: SP605 Evaluation Board Related Xilinx Documents Prior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources. See the following locations for additional documentation on Xilinx tools and solutions: • ISE: www.xilinx.com/ise • Answer Browser: www.xilinx.com/support • Intellectual Property: www.xilinx.com/ipcenter Detailed Description Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document
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Detailed Description Table 1-1: SP605 Features (Cont’d) Schematic Number Feature Notes Page 4 Linear BPI Flash x16 Numonyx JS28F256P30T95 19 SystemACE CompactFlash 5 XCCACE-TQ144I Controller 20 Socket 6 USB JTAG Conn. (USB Mini-B) USB JTAG Download Circuit 32 200 MHz OSC, oscillator socket, Clock Generation 13, 14 SMA connectors a. 200 MHz oscillator Epson 200 MHz 2.5V LVDS 14 7 b. Oscillator socket, single- MMD Components 2.5V 27 MHz 14 ended, LVCMOS c. SMA connectors SMA pair P(J41) / N(J38
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Chapter 1: SP605 Evaluation Board Table 1-1: SP605 Features (Cont’d) Schematic Number Feature Notes Page Power, Configuration, 14, 18, 20, Switches Pushbutton Switches 25 a. SP605 Power On-Off Slide 25 Switch b. FPGA Mode DIP Switch 18 17 c. System ACE CF 20 Configuration DIP Switch d. FPGA PROG, CPU Reset, and System ACE CF Reset 14, 20 Pushbutton Switches 18 FMC LPC Connector Samtec ASP-134603-01 10 a. Power Management 2x TI UCD9240PFC 21, 26 Controller 19 b. Mini-Fit Type 6-Pi
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Detailed Description I/O Voltage Rails There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP605 board is summarized in Table 1-2. Table 1-2: I/O Voltage Rail of FPGA Banks FPGA Bank I/O Voltage Rail 02.5V 12.5V 22.5V 31.5V References See the Xilinx Spartan-6 FPGA documentation f
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Chapter 1: SP605 Evaluation Board Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements U1 FPGA Pin FPGA Pin Number Board Connection for OCT ZIO P3 No Connect RZQ L6 100 ohms to GROUND Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory. Table 1-5: DDR3 Component Memory Connections Memory U42 U1 FPGA Schematic Net Name Pin Pin Number Pin Name K2 MEM1_A0 N3 A0 K1 MEM1_A1 P7 A1 K5 MEM1_A2 P3 A2 M6 MEM1_A3 N2 A3 H3 MEM1_A4 P8 A4 M3 MEM1_A5 P2 A5 L4 MEM1
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Detailed Description Table 1-5: DDR3 Component Memory Connections (Cont’d) Memory U42 U1 FPGA Schematic Net Name Pin Pin Number Pin Name T1 MEM1_DQ9 C3 DQ9 U3 MEM1_DQ10 A2 DQ13 U1 MEM1_DQ11 D7 DQ8 W3 MEM1_DQ12 A3 DQ15 W1 MEM1_DQ13 C8 DQ10 Y2 MEM1_DQ14 B8 DQ14 Y1 MEM1_DQ15 A7 DQ12 H2 MEM1_WE_B L3 WE_B M5 MEM1_RAS_B J3 RAS_B M4 MEM1_CAS_B K3 CAS_B L6 MEM1_ODT K1 ODT K4 MEM1_CLK_P J7 CLK_P K3 MEM1_CLK_N K7 CLK_N F2 MEM1_CKE K9 CKE N3 MEM1_LDQS_P F3 LDQS_P N1 MEM1_LDQS_N G3 LDQS_N V2 MEM1_UDQS_P
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Chapter 1: SP605 Evaluation Board 3. SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing an external SPI flash memory device. The SP605 SPI interface has two parallel connected configurati
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Detailed Description Table 1-6: SPI x4 Memory Connections SPI MEM U32 SPI HDR J17 U1 FPGA Schematic Net Name Pin Pin # Pin Name Pin # Pin Name AB2 FPGA_PROG_B – – 1 – T14 FPGA_D2_MISO3 1 IO3_HOLD_B 2 – R13 FPGA_D1_MISO2_R 9 IO2_WP_B 3 – AA3 SPI_CS_B – – 4 TMS AB20 FPGA_MOSI_CSI_B_MISO0 15 DIN 5 TDI AA20 FPGA_D0_DIN_MISO_MISO1 8 IO1_DOUT 6 TDO Y20 FPGA_CCLK 16 CLK 7 TCK – – – – 8 GND – – – – 9 VCC3V3 (1) J46.2 SPIX4_CS_B 7 CS_B – – Notes: 1. Not a U1 FPGA pin References See the Winbond Seri
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Chapter 1: SP605 Evaluation Board 4. Linear BPI Flash A Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 (Figure 1-5) provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear Flash is operated in asynchronous mode. For details on configuring the FPGA, see “Configuration Options.” X-Ref Target - Figure 1-5 U1 U25 ADDR, DATA, CTRL Numonyx Type P30 FPGA JS28F256P30 BPI Flash Interface UG526_05_092409 Figure 1-5: Linear BPI Flash
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Detailed Description Table 1-7: Linear Flash Connections (Cont’d) U25 BPI FLASH U1 FPGA Pin Schematic Net Name Pin Number Pin Name E22 FLASH_A16 55 A17 E20 FLASH_A17 18 A18 F22 FLASH_A18 17 A19 F21 FLASH_A19 16 A20 H19 FLASH_A20 11 A21 H18 FLASH_A21 10 A22 F20 FLASH_A22 9 A23 G19 FLASH_A23 26 A24 AA20 FPGA_D0_DIN_MISO_MISO1 34 DQ0 R13 FPGA_D1_MISO2 36 DQ1 T14 FPGA_D2_MISO3 39 DQ2 AA6 FLASH_D3 41 DQ3 AB6 FLASH_D4 47 DQ4 Y5 FLASH_D5 49 DQ5 AB5 FLASH_D6 51 DQ6 W9 FLASH_D7 53 DQ7 T7 FLASH_D8 35 D
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Chapter 1: SP605 Evaluation Board FPGA Design Considerations for the Configuration Flash The SP605 has the P30 BPI flash connected to the FPGA dual use configuration pins and is not shared. It can be used to configure the FPGA, and then controlled post-configuration via the FPGA fabric. After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to read/write code or data. When the FPGA design does not use the configuration flash, the FPGA d
