Resumen del contenido incluido en la página 1
ML605 Hardware
User Guide
User Guide [optional]
UG UG53 534 4 ( (v v1 1..2 2..1 1) ) Ja Jan nu uar ary 21 y 21, 20 , 2010 10 [optional]
Resumen del contenido incluido en la página 2
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any li
Resumen del contenido incluido en la página 3
Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 1: ML605 Evaluation Board Overview . . . . . . . .
Resumen del contenido incluido en la página 4
FPGA_PROG_B Pushbutton SW4 (Active-Low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SYSACE_RESET_B Pushbutton SW3 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 System ACE CF CompactFlash Image Select DIP Switch S1. . . . . . . . . . . . . . . . . . . . . . 55 Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2 . . . . . . . . . . . 56 19. VITA 57.1 FMC HPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resumen del contenido incluido en la página 5
Preface About This Guide This manual accompanies the Virtex®-6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “ML605 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the ML605 board. • Appendix A, “Default Switch and Jumper Settings.” • Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout.”
Resumen del contenido incluido en la página 6
Preface: About This Guide • Virtex-6 FPGA Memory Resources User Guide The functionality of the block RAM and FIFO are described in this user guide. • Virtex-6 FPGA SelectIO Resources User Guide This guide describes the SelectIO™ resources available in all Virtex-6 devices. • Virtex-6 FPGA GTX Transceivers User Guide This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the XC6VLX760. • Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide This guide describes the de
Resumen del contenido incluido en la página 7
Chapter 1 ML605 Evaluation Board Overview The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex®-6 XC6VLX240T-1FFG1156 FPGA. The ML605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART. Additional user desired features can be added through mezzanine cards attached to the o
Resumen del contenido incluido en la página 8
Chapter 1: ML605 Evaluation Board Features The ML605 provides the following features: • 1. Virtex-6 XC6VLX240T-1FFG1156 FPGA • 2. 512 MB DDR3 Memory SODIMM • 3. 128 Mb Platform Flash XL • 4. 32 MB Linear BPI Flash • 5. System ACE CF and CompactFlash Connector • 6. USB JTAG • 7. Clock Generation ♦ Fixed 200 MHz oscillator (differential) ♦ Socketed 2.5V oscillator (single-ended) ♦ SMA connectors (differential) ♦ SMA connectors for MGT clocking • 8. Multi-Gigabit Transceivers (GTX MGTs) ♦ FMC - HPC
Resumen del contenido incluido en la página 9
Overview • 16. Status LEDs ♦ Ethernet status ♦ FPGA INIT ♦ FPGA DONE ♦ System ACE CF Status • 17. User I/O ♦ USER LED Group 1 - GPIO (8) ♦ USER LED Group 2 - directional (5) ♦ User pushbuttons - directional (5) ♦ CPU reset pushbutton ♦ User DIP switch - GPIO (8-pole) ♦ User SMA GPIO connectors (2) ♦ LCD character display (16 characters x 2 lines) • 18. Switches ♦ Power on/off slide switch ♦ System ACE CF reset pushbutton ♦ System ACE CF bitstream image select DIP switch ♦ Configuration MODE DIP
Resumen del contenido incluido en la página 10
Chapter 1: ML605 Evaluation Board Block Diagram Figure 1-1 shows a high-level block diagram of the ML605 and its peripherals. X-Ref Target - Figure 1-1 JTAG USB Mini-B System ACE CF VITA 57.1 FMC VITA 57.1 FMC USB JTAG Circuit S.A. CompactFlash HPC Connector LPC Connector S.A. 8-bit MPU I/F BANK32 BANK12, 13 BANK15,16 SYSMON I/F Platform Flash BANK14,22 BANK34,116 INIT, DONE LEDs BANK24 Linear BPI Flash BANK23,24 PROG PB, MODE SW BANK34 BANK112,113 BANK0 IIC Bus IIC EEPROM DVI Codec BANK32 BANK3
Resumen del contenido incluido en la página 11
Detailed Description Detailed Description Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document. X-Ref Target - Figure 1-2 18a 13 20 19 16c 13 17a 21c 23 10 7b 7c 17e 18d 18c 17d 16b 21d 5 2 18b 12 7d 6 16a 1 22 21a 21b 11 8 3 17f 17c 21a 14 8 4 17b 7a 9 (on backside) 15 UG534_02_123009 Figure 1-2: ML605 Board Photo The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1. Table 1-1: ML605 Fe
Resumen del contenido incluido en la página 12
Chapter 1: ML605 Evaluation Board Table 1-1: ML605 Features (Cont’d) Schematic NumberFeature Notes Page 200 MHz OSC, oscillator socket, SMA Clock generation 30 connectors a. 200 MHz oscillator (on Epson 200 MHz 2.5V LVDS OSC 30 backside) 7 b. Oscillator socket, single- MMD Components 66 MHz 2.5V 30 ended c. SMA connectors SMA pair 30 d. MGT REFCLK SMA SMA pair 30 connectors 8GTX RX/TX port SMA x4 30 PCIe Gen1 (8-lane), 9 Card edge connector, 8-lane 21 Gen2 (4-lane) 10 SFP connector and cage
Resumen del contenido incluido en la página 13
Detailed Description Table 1-1: ML605 Features (Cont’d) Schematic NumberFeature Notes Page Switches 13, 25, 39 a. Power On/Off Slide switch 39 b. FPGA_PROG_B active-Low 13 18 pushbutton c. System ACE CF Image 4-pole DIP switch (active-High) 25 Select d. Mode Switch 6-pole DIP switch (active-High) 25 19 FMC - HPC connector Samtec ASP-134486-01 16 -19 20 FMC - LPC connector Samtec ASP-134603-01 20 Power management 35 - 44 a. PMBus controllers 2 x TI UCD9240PFC 35, 40 b. Voltage regulators 36-38
Resumen del contenido incluido en la página 14
Chapter 1: ML605 Evaluation Board The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by setting M[2:0] options 010, 101 and 110 shown in Table 1-2. Table 1-2: Virtex-6 FPGA Configuration Modes (1) Configuration Mode M[2:0] Bus Width CCLK Direction (2) Master Serial 000 1Output (2) Master SPI 001 1Output (2) Master BPI-Up 010 8, 16 Output (2) Master BPI-Down 011 8, 16 Output (2) Master SelectMAP 100 8, 16 Output JTAG 101 1 Input (TCK) Slave SelectMAP 110 8, 16, 32 In
Resumen del contenido incluido en la página 15
Detailed Description Table 1-3: Voltage Rails (Cont’d) U1 FPGA Bank I/O Rail Voltage Bank 24 VCC2V5_FPGA 2.5V Bank 25 VCC1V5_FPGA 1.5V Bank 26 VCC1V5_FPGA 1.5V Bank 32 VCC2V5_FPGA 2.5V Bank 33 VCC2V5_FPGA 2.5V Bank 34 VCC2V5_FPGA 2.5V Bank 35 VCC1V5_FPGA 1.5V Bank 36 VCC1V5_FPGA 1.5V Notes: 1. The VITA 57.1 specification stipulates that the Bank 12 voltage named FMC_VIO_B_M2C is supplied by the FMC card plugged onto the relevant FMC connector (ML605 J64). FMC_VIO_B_M2C cannot exceed the base
Resumen del contenido incluido en la página 16
Chapter 1: ML605 Evaluation Board Table 1-4: DDR3 SODIMM Connections (Cont’d) J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name A15 DDR3_A6 90 A6 B15 DDR3_A7 86 A7 G15 DDR3_A8 89 A8 F15 DDR3_A9 85 A9 M16 DDR3_A10 107 A10/AP M15 DDR3_A11 84 A11 H15 DDR3_A12 83 A12_BC_N J15 DDR3_A13 119 A13 D15 DDR3_A14 80 A14 C15 DDR3_A15 78 A15 K19 DDR3_BA0 109 BA0 J19 DDR3_BA1 108 BA1 L15 DDR3_BA2 79 BA2 J11 DDR3_D0 5 DQ0 E13 DDR3_D1 7 DQ1 F13 DDR3_D2 15 DQ2 K11 DDR3_D3 17 DQ3 L11 DDR3_D4 4 DQ4 K
Resumen del contenido incluido en la página 17
Detailed Description Table 1-4: DDR3 SODIMM Connections (Cont’d) J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name G12 DDR3_D20 40 DQ20 G13 DDR3_D21 42 DQ21 F14 DDR3_D22 50 DQ22 H14 DDR3_D23 52 DQ23 C19 DDR3_D24 57 DQ24 G20 DDR3_D25 59 DQ25 E19 DDR3_D26 67 DQ26 F20 DDR3_D27 69 DQ27 A20 DDR3_D28 56 DQ28 A21 DDR3_D29 58 DQ29 E22 DDR3_D30 68 DQ30 E23 DDR3_D31 70 DQ31 G21 DDR3_D32 129 DQ32 B21 DDR3_D33 131 DQ33 A23 DDR3_D34 141 DQ34 A24 DDR3_D35 143 DQ35 C20 DDR3_D36 130 DQ36 D20 DDR3_D37
Resumen del contenido incluido en la página 18
Chapter 1: ML605 Evaluation Board Table 1-4: DDR3 SODIMM Connections (Cont’d) J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name E24 DDR3_D54 174 DQ54 G25 DDR3_D55 176 DQ55 F28 DDR3_D56 181 DQ56 B31 DDR3_D57 183 DQ57 H29 DDR3_D58 191 DQ58 H28 DDR3_D59 193 DQ59 B30 DDR3_D60 180 DQ60 A30 DDR3_D61 182 DQ61 E29 DDR3_D62 192 DQ62 F29 DDR3_D63 194 DQ63 E11 DDR3_DM0 11 DM0 B11 DDR3_DM1 28 DM1 E14 DDR3_DM2 46 DM2 D19 DDR3_DM3 63 DM3 B22 DDR3_DM4 136 DM4 A26 DDR3_DM5 153 DM5 A29 DDR3_DM6 170 DM
Resumen del contenido incluido en la página 19
Detailed Description Table 1-4: DDR3 SODIMM Connections (Cont’d) J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name C30 DDR3_DQS7_P 188 DQS7_P F18 DDR3_ODT0 116 ODT0 E17 DDR3_ODT1 120 ODT1 E18 DDR3_RESET_B 30 RESET_B K18 DDR3_S0_B 114 S0_B K17 DDR3_S1_B 121 S1_B D17 DDR3_TEMP_EVENT 198 EVENT_B B17 DDR3_WE_B 113 WE_B C17 DDR3_CAS_B 115 CAS_B L19 DDR3_RAS_B 110 RAS_B M18 DDR3_CKE0 73 CKE0 M17 DDR3_CKE1 74 CKE1 H18 DDR3_CLK0_N 103 CK0_N G18 DDR3_CLK0_P 101 CK0_P L16 DDR3_CLK1_N 104
Resumen del contenido incluido en la página 20
Chapter 1: ML605 Evaluation Board 3. 128 Mb Platform Flash XL A 128 Mb Xilinx XCF128X-FTG64C Platform Flash XL device is used with an onboard 47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid as required by the PCI Express Card Electromechanical Specification. This allows the PCIe interface to be recognized and enumerated when plugged into a host PC. To achieve the fastest configuration speed, the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MH
