Resumen del contenido incluido en la página 1
USER'S MANUAL
μPD750008
4 BIT SINGLE-CHIP MICROCOMPUTER
μPD750004
μPD750006
μPD750008
μPD75P0016
Document No. U10740EJ2V0UM00 (2nd edition)
(Previous No. IEU-1421)
Date Published April 1996 P
Printed in Japan
© 1995
Resumen del contenido incluido en la página 2
1 GENERAL 2 PIN FUNCTIONS 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 4 INTERNAL CPU FUNCTIONS 5 PERIPHERAL HARDWARE FUNCTIONS 6 INTERRUPT AND TEST FUNCTIONS 7 STANDBY FUNCTION 8 RESET FUNCTION WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) 9 10 MASK OPTION 11 INSTRUCTION SET FUNCTIONS OF THE μPD75008, μPD750008, AND μPD75P0016 A DEVELOPMENT TOOLS B MASK ROM ORDERING PROCEDURE C INSTRUCTION INDEX D HARDWARE INDEX E F RIVISION HISTORY
Resumen del contenido incluido en la página 3
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The information in this document is subject to change without notice. No part of this document may be copied or reproduced
Resumen del contenido incluido en la página 4
Major Changes Page Description All The 44-pin plastic QFP package has been changed from μPD750008GB-xxx-3B4 to μPD750008GB-xxx-3BS-MTX. The μPD75P0016 under development has been changed to the already-developed μPD75P0016. The input withstand voltage at ports 4 and 5 during open drain has been changed from 12 V to 13 V. Preface English-version document numbers have been added to "Related documents." p.4 The format of the table in Section 1.3 has been changed. p.45 The caution in using Mk II mode
Resumen del contenido incluido en la página 5
PREFACE Readers This manual is intended for engineers who want to learn the capabilities of the μPD750004, μPD750006, μPD750008, and μPD75P0016 to develop application systems based on them. Purpose The purpose of this manual is to help users understand the hardware capabilities (shown below) of the μPD750004, μPD750006, μPD750008, and μPD75P0016. Configuration This manual is roughly divided as follows: • General • Pin functions • Architecture feature and memory map • Internal CPU functions • Per
Resumen del contenido incluido en la página 6
Notation Data bit significance : Higher-order bits on the left side Lower-order bits on the right side Active low : xxx (Pin and signal names are overscored.) Memory map address : Low-order address on the upper side High-order address on the lower side Note : Explanation of an indicated part of text Caution : Information requesting the user's special attention Remark : Supplementary information Important and emphasized matter : Described in bold face Numeric value : Binary .................. xxx
Resumen del contenido incluido en la página 7
Related documents Some documents are preliminary editions, but they are not so specified in the tables * below. Documents related to devices Document Number Document Name Japanese English μPD750004, 750006, 750008 Data Sheet U10738J IC-3647 μPD75P0016 Data Sheet U10328J To be prepared μPD750008 User’s Manual U10740J (This manual) IEU-1421 μPD750008 Instruction List IEM-5593 — 75XL Series Selection Guide U10453J U10453E Documents related to development tools Document Number Document Name Japanese
Resumen del contenido incluido en la página 8
[MEMO]
Resumen del contenido incluido en la página 9
CONTENTS CHAPTER 1 GENERAL ......................................................................................................................... 1 1.1 FUNCTION OVERVIEW ......................................................................................... 2 1.2 ORDERING INFORMATION................................................................................... 3 1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS............................................. 4 1.4 BLOCK DIAGRAM ...................
Resumen del contenido incluido en la página 10
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ....................................... 21 3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES .................. 21 3.1.1 Data Memory Bank Structure .................................................................... 21 3.1.2 Data Memory Addressing Modes .............................................................. 23 3.2 GENERAL REGISTER BANK CONFIGURATION ................................................. 34 3.3 MEMORY-MAPPED I/O ........
Resumen del contenido incluido en la página 11
5.3.5 Operation of the Watchdog Timer ............................................................. 102 5.3.6 Other Functions ......................................................................................... 103 5.4 CLOCK TIMER ........................................................................................................ 105 5.4.1 Configuration of the Clock Timer .............................................................. 106 5.4.2 Clock Mode Register .......................
Resumen del contenido incluido en la página 12
CHAPTER 8 RESET FUNCTION ........................................................................................................... 225 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ................................... 229 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY .................................................................................... 230 9.2 WRITING TO THE PROGRAM MEMORY ............................................................. 230 9.3 READ
Resumen del contenido incluido en la página 13
APPENDIX A FUNCTIONS OF THE μPD75008, μPD750008, AND μPD75P0016 ............................ 299 APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 301 APPENDIX C MASKED ROM ORDERING PROCEDURE................................................................... 309 APPENDIX D INSTRUCTION INDEX .................................................................................................... 311 D.1 INSTRUCTION
Resumen del contenido incluido en la página 14
LIST OF FIGURES (1/4) Figure No. Title Page 2-1 Pin Input/Output Circuits .................................................................................................. 18 3-1 Use of MBE = 0 Mode and MBE = 1 Mode ..................................................................... 22 3-2 Data Memory Organization and Addressing Range of Each Addressing Mode ............ 24 3-3 Updating Static RAM Addresses......................................................................................
Resumen del contenido incluido en la página 15
LIST OF FIGURES (2/4) Figure No. Title Page 5-9 I/O Timing Chart of Digital I/O Ports ................................................................................ 82 5-10 ON Timing Chart of Built-in Pull-Up Resistor Connected by Software.......................... 83 5-11 Block Diagram of the Clock Generator ............................................................................ 84 5-12 Format of the Processor Clock Control Register.......................................................
Resumen del contenido incluido en la página 16
LIST OF FIGURES (3/4) Figure No. Title Page 5-45 Operations of RELT and CMDT ....................................................................................... 141 5-46 Transfer Bit Switching Circuit ........................................................................................... 141 5-47 Example of Two-Wire Serial I/O System Configuration .................................................. 144 5-48 Timing of Two-Wire Serial I/O Mode................................................
Resumen del contenido incluido en la página 17
LIST OF FIGURES (4/4) Figure No. Title Page 5-81 Format of the Bit Sequential Buffer ................................................................................. 181 6-1 Block Diagram of Interrupt Control Circuit ....................................................................... 184 6-2 Interrupt Vector Table....................................................................................................... 185 6-3 Interrupt Priority Specification Register ..........................
Resumen del contenido incluido en la página 18
LIST OF TABLES (1/2) Table No. Title Page 1-1 Features of the Products .................................................................................................. 1 2-1 Digital I/O Port Pins .......................................................................................................... 9 2-2 Non-Port Pin Functions .................................................................................................... 11 2-3 Connection of Unused Pins................................
Resumen del contenido incluido en la página 19
LIST OF TABLES (2/2) Table No. Title Page 7-1 Operation Statuses in the Standby Mode ........................................................................ 216 7-2 Selection of a Wait Time with BTM.................................................................................. 219 8-1 Status of the Hardware after a Reset .............................................................................. 226 10-1 Selecting Mask Option of Pin .......................................................
Resumen del contenido incluido en la página 20
[MEMO] - xii -
