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HC05RC16GRS/D
REV. 3.0
MC68HC05RC8
MC68HC05RC16
General Release Specification
October 24, 1996
CSIC MCU Design Center
Austin, Texas
NON-DISCLOSURE AGREEMENT REQUIRED
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General Release Specification Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
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General Release Specification — MC68HC05RC16 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Section 3. Central Processor Unit . . . . . . . . . . . . . . . . . 33 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 6. Low-Power Modes . . . . . . . . . . . . .
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List of Sections General Release Specification MC68HC05RC16 — Rev. 3.0 4 List of Sections MOTOROLA
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General Release Specification — MC68HC05RC16 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 Signal Desc
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Table of Contents Section 3. Central Processor Unit 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5 Condition Code Register. . . . . . . . . . . . . . . .
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Table of Contents 5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .49 5.5.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.3 COP During Stop Mode . . . . . . . . . . . . . . . .
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Table of Contents Section 8. Core Timer 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.3 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .63 8.4 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.5 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .66 8.6 Timer During Wait
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Table of Contents Section 10. Instruction Set 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 10.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Section 12. Mechanical Specifications 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.3 28-Pin Plastic Dual In-Line Package (Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . .
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General Release Specification — MC68HC05RC16 List of Figures Figure Title Page 1-1 MC68HC05RC16 Block Diagram . . . . . . . . . . . . . . . . . . . . .18 1-2 28-Pin DIP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1-3 28-Pin SOIC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1-4 44-Pin PLCC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1-5 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures Figure Title Page 9-1 Carrier Modulator Transmitter Module Block Diagram . . . . .69 9-2 Carrier Generator Block Diagram. . . . . . . . . . . . . . . . . . . . .70 9-3 Carrier Generator Data Register CHR1 . . . . . . . . . . . . . . . .72 9-4 Carrier Generator Data Register CLR1 . . . . . . . . . . . . . . . .72 9-5 Carrier Generator Data Register CHR2 . . . . . . . . . . . . . . . .72 9-6 Carrier Generator Data Register CLR2 . . . . . . . . . . . . . . . .73 9-7 Modulator Block
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General Release Specification — MC68HC05RC16 List of Tables Table Title Page 4-1 Vector Address for Interrupts and Reset ................................38 5-1 COP Watchdog Timer Recommendations .............................50 7-1 I/O Pin Functions ....................................................................59 8-1 RTI and COP Rates at 4.096 MHz Oscillator .........................64 10-1 Register/Memory Instructions.................................................90 10-2 Read-Modify-Writ
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List of Tables General Release Specification MC68HC05RC16 — Rev. 3.0 14 List of Tables MOTOROLA
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General Release Specification — MC68HC05RC16 Section 1. General Description 1.1 Contents 1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.1 V and V . . . . .
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General Description 1.2 Introduction The MC68HC05RC16 is a low-cost addition to the M68HC05 Family of microcontrollers (MCUs) and is suitable for remote control applications. This device contains the HC05 central processing unit (CPU) core, including the 14-stage core timer with real-time interrupt (RTI) and computer operating properly (COP) watchdog systems. On-chip peripherals include a carrier modulator transmitter. The 16-kbyte memory map has 15,936 bytes of user ROM and 352 bytes of RAM. T
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General Description Features • Low-Power Reset Pin • 20 Bidirectional I/O Lines (Four Additional I/O Lines Available for Bond Out in 44-Lead PLCC Package) • Mask Programmable Pullups and Interrupts on Eight Port Pins (PB0–PB7) • High-Current Infrared (IR) Drive Pin • High-Current Port Pin (PC0) • Power-Saving Stop and Wait Modes • Mask Selectable Options: – COP Watchdog Timer – STOP Instruction Disable – Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger – Port B Pullups for Keyscan •
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General Description OSC2 CARRIER OSCILLATOR MODULATOR IRO OSC1 TRANSMITTER IRQEN ÷ 2 V DD INTERNAL PROCESSOR PC0 V SS CLOCK PC1 CORE TIMER PC2 COP RTI SYSTEM SYSTEM SYSTEM PC3 PC4* PC5* PC6* RESET PC7* LPRST CPU ALU CONTROL PA0 PA1 M68HC05 CPU PA2 CPU REGISTERS ACCUMULATOR PA3 IRQEN INDEX REGISTER PA4 0 0 0 0 1 1 STACK POINTER 0 PA5 0 0 PROGRAM COUNTER IRQ PA6 CONDITION CODE REGISTER 1 H I N Z C 1 1 PA7 PB0 PB1 SRAM — 352 BYTES PB2 PB3 ROM — 15,936 BYTES PB4 PB5 PB6 BURN-IN ROM — 64 BYTES PB7 *
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General Description Mask Options 1.4 Mask Options There are 11 total mask options on the MC68HC05RC16 including: • Eight port B pullups • IRQ sensitivity • COP enable/disable • STOP enable/disable These are nonprogrammable options in that they are selected at the time of code submission (when masks are made). These options are as follows: PB7PU — Port B7 Pullup/Interrupt This bit enables or disables the pullup/interrupt on port B, bit 7. 1 = Enables the pullup/interrupt 0 = Disables the pullup/
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General Description PB2PU — Port B2 Pullup/Interrupt This option enables or disables the pullup/interrupt on port B, bit 2. 1 = Enables pullup/interrupt 0 = Disables pullup/interrupt PB1PU — Port B1 Pullup/Interrupt This option enables or disables the pullup/interrupt on port B, bit 1. 1 = Enables pullup/interrupt 0 = Disables pullup/interrupt PB0PU — Port B0 Pullup/Interrupt This option enables or disables the pullup/interrupt on port B, bit 0. 1 = Enables pullup/interrupt 0 = Disables pullup/i
