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Cover
88F6281
Integrated Controller
Hardware Specifications
Doc. No. MV-S104859-U0, Rev. E
December 2, 2008, Preliminary
Marvell. Moving Forward Faster Document Classification: Proprietary Information
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88F6281 Hardware Specifications Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary Technical Publication: 0.xx
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88F6281 Integrated Controller Hardware Specifications PRODUCT OVERVIEW ® The Marvell 88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell ™ proprietary, ARMv5TE-compliant, high-speed Sheeva CPU core. The CPU core integrates a 256 KB L2 cache. Processor High Speed I/0 Sheeva™ CPU Core L2 PCI Express PCI Express x1 Cache JTAG Interface 16 KB-I, 16 KB-D 256 KB Up to 1.5 GHz Dual SATA ports SATA Memory USB 2.0 USB 2.0 port DDR
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88F6281 Hardware Specifications FEATURES The 88F6281 includes: • DDR SDRAM with a clock ratio of 1:N and 2:N • High-performance CPU core, running at up to between the DDR SDRAM and the CPU core, 1.5 GHz, with integrated, four-way, set-associative respectively L1 16-KB I-cache/16-KB D-cache and unified, • SSTL 1.8V I/Os 256-KB, four-way, set-associative L2 cache • Auto calibration of I/Os output impedance • High-bandwidth dual-port DDR2 memory interface • Supports
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Features • Priority queuing on receive based on Destination - Backwards compatible with SATA I devices Address (DA), VLAN Tag, and IP TOS • Supports SATA II Phase 2 advanced features • Layer 2/3/4 frame encapsulation detection - 3 Gbps (Gen2i) SATA II speed • TCP/IP checksum on receive and transmit - Port Multiplier (PM)—Performs FIS-based • Supports proprietary 200 Mbps Marvell MII (MMII) switching, as defined in SATA working group PM interface definition • Supports four modes: - Port Selecto
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88F6281 Hardware Specifications 2 I S-specific features MPEG Transport Stream (TS) interface • Sample rates of 44.1/48/96 kHz • ISO/IEC 13818-1 standard compliant 2 2 • Supports any one of the following modes: • I S input and I S output operate at the same - Parallel (8 bit) input sample rate - Parallel output • 16/24-bit depths 2 2 - Two independent serial interfaces • I S in and I S out support independent bit depths • Data rate up to 80 Mbps (16 bit/24 bit) 2
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Features SATA Port HDD Multiplier PCI Express On Board DDR2 Mini Card Wi-Fi x16 SPI Flash (op.) SD Card 88F6281 x8 USB Host NAND Flash TDM Audio GbE PHY FXS FXO A/D – D/A Usage Model Example: VoIP Gateway Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E December 2, 2008, Preliminary Document Classification: Proprietary Information Page 7
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88F6281 Hardware Specifications Table of Contents Product Overview.......................................................................................................................................3 Features.......................................................................................................................................................4 Preface......................................................................................................
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Table of Contents 8 Electrical Specifications (Preliminary) ......................................................................................75 8.1 Absolute Maximum Ratings ............................................................................................................................75 8.2 Recommended Operating Conditions .............................................................................................................77 8.3 Thermal Power Dissipation ................
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88F6281 Hardware Specifications List of Tables 1 Pin and Signal Descriptions ............................................................................................................17 Table 1: Pin Functions and Assignments Table Key ......................................................................................19 Table 2: Interface Pin Prefix Codes ...............................................................................................................
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List of Tables 7 JTAG Interface ..................................................................................................................................73 Table 33: Supported JTAG Instructions............................................................................................................73 Table 34: IDCODE Register Map .....................................................................................................................74 8 Electrical Specifications (Prelimin
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88F6281 Hardware Specifications 10 Package ...........................................................................................................................................130 Table 73: HSBGA 288-pin Package Dimensions ...........................................................................................131 11 Part Order Numbering/Package Marking......................................................................................132 Table 74: 88F6281 Pa
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List of Figures List of Figures 1 Pin and Signal Descriptions ........................................................................................................... 17 Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18 2 Unused Interface Strapping............................................................................................................ 49 3 88F6281 Pin Map and Pin List .........
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88F6281 Hardware Specifications Figure 28: Inter-IC Sound (I2S) Test Circuit ....................................................................................................107 Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................108 Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................108 Figure 31: TDM Interfa
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Preface About this Document Preface About this Document This datasheet provides the hardware specifications for the 88F6281 integrated controller. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications. This datasheet is intended to be the basic source of information for designers of new systems. In this document, the “88F6281” is often referred to as the “device”. Related Documentation The following documen
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88F6281 Hardware Specifications RFC 1321 (The MD5 Message-Digest Algorithm) RFC 1851 – The ESP Triple DES Transform RFC 2104 (HMAC: Keyed-Hashing for Message Authentication). RFC 2405 – The ESP DES-CBC Cipher Algorithm With Explicit IV IEEE standard, 802.3-2000 Clause 14 ANSI standard X3.263-1995 See the Marvell Extranet website for the latest product documentation. Document Conventions The following conventions are used in this document:
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Pin and Signal Descriptions 1 Pin and Signal Descriptions This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality. Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E December 2, 2008, Preliminary Document Classification: Proprietary Information Page 17
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88F6281 Hardware Specifications 1.1 Pin Logic Figure 1: 88F6281 Pin Logic Diagram REF_CLK_XIN VDD XOUT VDD_CPU VDDO SYSRSTn VDD_GE_A TP VDD_GE_B Misc. VDD_M ISET VSS RESERVED CPU_PLL_AVDD MRn NC CPU_PLL_AVSS CORE_PLL_AVDD PEX_CLK_P CORE_PLL_AVSS Power PEX_CLK_N XTAL_AVDD PEX_TX_P XTAL_AVSS PEX_TX_N PEX_AVDD PCI Express PEX_RX_P SATA0_AVDD PEX_RX_N SATA1_AVDD PEX_ISET USB_AVDD RTC_AVDD RTC_AVSS USB_DP USB SSCG_AVDD USB_DM SSCG_AVSS VHV GE_TXCLKOUT MPP[49:0] MPP
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Pin and Signal Descriptions Pin Descriptions 1.2 Pin Descriptions This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes. Table 1 defines the abbreviations and acronyms used in the pin description tables. Table 1: Pin Functions and Assignments Table Key Term Definition [n] n - Represents the SERDES pair number Represents port number when there are more than one ports Analog A
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88F6281 Hardware Specifications Table 2: Interface Pin Prefix Codes (Continued) Interface Prefix RTC RTC_ NAND Flash NF_ MPP N/A TWSI TW_ UART UA0_ UA1_ Audio AU_ SPI SPI_ SDIO SD_ TDM TDM_ PTP PTP_ Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell Page 20 Document Classification: Proprietary Information December 2, 2008, Preliminary
